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fix(qemu): statically allocate bitlocks array

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gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks, allocate a static array and pass its address to
gpt_runtime_init(). This frees up a little bit of space formerly
reserved for alignment of the GPT.

Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
This commit is contained in:
Jean-Philippe Brucker 2025-02-11 14:10:34 +00:00
parent 991f5360b6
commit a32a77f9c7
6 changed files with 40 additions and 43 deletions
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1
include/plat/common/common_def.h
View file

@ -45,6 +45,7 @@
#define SZ_2G UL(0x80000000)
#define SZ_1T UL(0x10000000000)
#define SZ_4T UL(0x40000000000)
#define SZ_1P UL(0x4000000000000)
#else /* !__aarch64__ */

31
plat/qemu/common/qemu_bl31_setup.c
View file

@ -46,6 +46,30 @@
MT_DEVICE | MT_RW | EL3_PAS)
#endif
#if ENABLE_RME
#if (RME_GPT_BITLOCK_BLOCK == 0)
#define BITLOCK_BASE UL(0)
#define BITLOCK_SIZE UL(0)
#else
/*
* Number of bitlock_t entries in the gpt_bitlock array for this platform's
* Protected Physical Size. One 8-bit bitlock_t entry covers
* 8 * RME_GPT_BITLOCK_BLOCK * 512MB.
*/
#if (PLAT_QEMU_PPS > (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8)))
#define BITLOCKS_NUM (PLAT_QEMU_PPS / \
(RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8)))
#else
#define BITLOCKS_NUM 1
#endif
static bitlock_t gpt_bitlock[BITLOCKS_NUM];
#define BITLOCK_BASE (uintptr_t)gpt_bitlock
#define BITLOCK_SIZE sizeof(gpt_bitlock)
#endif /* RME_GPT_BITLOCK_BLOCK */
#endif /* ENABLE_RME */
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
@ -202,9 +226,8 @@ static void bl31_plat_gpt_setup(void)
* 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the
* moment we use a 8KB table, which covers 1TB of RAM (40-bit PA).
*/
if (gpt_init_l0_tables(PLATFORM_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE,
PLAT_QEMU_L0_GPT_SIZE +
PLAT_QEMU_GPT_BITLOCK_SIZE) < 0) {
if (gpt_init_l0_tables(PLAT_QEMU_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE,
PLAT_QEMU_L0_GPT_SIZE) < 0) {
ERROR("gpt_init_l0_tables() failed!\n");
panic();
}
@ -260,7 +283,7 @@ void bl31_plat_arch_setup(void)
* stage, so there is no need to provide any PAS here. This function
* sets up pointers to those tables.
*/
if (gpt_runtime_init() < 0) {
if (gpt_runtime_init(BITLOCK_BASE, BITLOCK_SIZE) < 0) {
ERROR("gpt_runtime_init() failed!\n");
panic();
}

17
plat/qemu/qemu/include/platform_def.h
View file

@ -342,22 +342,16 @@
* Tables
*/
#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
(PLAT_QEMU_L0_GPT_SIZE + \
PLAT_QEMU_GPT_BITLOCK_SIZE))
#define PLAT_QEMU_L0_GPT_SIZE (2 * PAGE_SIZE)
/* Two pages so the L0 GPT is naturally aligned. */
#define PLAT_QEMU_GPT_BITLOCK_SIZE (2 * PAGE_SIZE)
PLAT_QEMU_L0_GPT_SIZE)
#define PLAT_QEMU_L0_GPT_SIZE SZ_8K
#define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
PLAT_QEMU_L1_GPT_SIZE)
#define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \
PLAT_QEMU_L1_GPT_SIZE - 1U)
#define PLAT_QEMU_L1_GPT_SIZE UL(0x00100000) /* 1MB */
#define PLAT_QEMU_L1_GPT_SIZE SZ_1M
#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
PLAT_QEMU_L0_GPT_SIZE + \
PLAT_QEMU_GPT_BITLOCK_SIZE)
PLAT_QEMU_L0_GPT_SIZE)
#ifndef __ASSEMBLER__
/* L0 table greater than 4KB must be naturally aligned */
@ -379,8 +373,7 @@ CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0,
#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
PLAT_QEMU_L0_GPT_BASE, \
PLAT_QEMU_L0_GPT_SIZE + \
PLAT_QEMU_GPT_BITLOCK_SIZE, \
PLAT_QEMU_L0_GPT_SIZE, \
MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \

3
plat/qemu/qemu/include/qemu_pas_def.h
View file

@ -103,7 +103,8 @@
GPT_GPI_REALM)
/* Cover 1TB with L0GTP */
#define PLATFORM_GPCCR_PPS GPCCR_PPS_1TB
#define PLAT_QEMU_GPCCR_PPS GPCCR_PPS_1TB
#define PLAT_QEMU_PPS SZ_1T
/* GPT Configuration options */
#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS

28
plat/qemu/qemu_sbsa/include/platform_def.h
View file

@ -405,24 +405,8 @@
*/
#define PLAT_QEMU_L0_GPT_SIZE (8 * PAGE_SIZE)
#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
(PLAT_QEMU_L0_GPT_SIZE + \
PLAT_QEMU_GPT_BITLOCK_SIZE + \
PLAT_QEMU_GPT_ALIGNMENT))
PLAT_QEMU_L0_GPT_SIZE)
#if RME_GPT_BITLOCK_BLOCK
/*
* 4TB / (RME_GPT_BITLOCK_BLOCK * 512M * 8) == 1024
*/
#define PLAT_QEMU_GPT_BITLOCK_SIZE (1 * PAGE_SIZE)
/*
* PLAT_QEMU_L0_GPT_SIZE is 8 pages and PLAT_QEMU_GPT_BITLOCK_SIZE
* is 1 page. As such we need 7 pages to have an 8 page alignment.
*/
#define PLAT_QEMU_GPT_ALIGNMENT (7 * PAGE_SIZE)
#else /* RME_GPT_BITLOCK_BLOCK */
#define PLAT_QEMU_GPT_BITLOCK_SIZE 0
#define PLAT_QEMU_GPT_ALIGNMENT 0
#endif /* RME_GPT_BITLOCK_BLOCK */
/*
* If we have 1TB of RAM and each L1GPT covers 1GB, we need 1024 L1GPTs. With
@ -433,14 +417,10 @@
#define PLAT_QEMU_L1_GPT_SIZE UL(0x08020000)
#define PLAT_QEMU_L1_GPT_BASE (BL_RAM_BASE + BL_RAM_SIZE - \
PLAT_QEMU_L1_GPT_SIZE)
#define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \
PLAT_QEMU_L1_GPT_SIZE - 1U)
#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
PLAT_QEMU_L0_GPT_SIZE + \
PLAT_QEMU_GPT_BITLOCK_SIZE + \
PLAT_QEMU_GPT_ALIGNMENT)
PLAT_QEMU_L0_GPT_SIZE)
#ifndef __ASSEMBLER__
/* L0 table greater than 4KB must be naturally aligned */
@ -462,9 +442,7 @@ CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0,
#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
PLAT_QEMU_L0_GPT_BASE, \
(PLAT_QEMU_L0_GPT_SIZE + \
PLAT_QEMU_GPT_BITLOCK_SIZE + \
PLAT_QEMU_GPT_ALIGNMENT), \
(PLAT_QEMU_L0_GPT_SIZE), \
MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \

3
plat/qemu/qemu_sbsa/include/qemu_sbsa_pas_def.h
View file

@ -58,7 +58,8 @@
GPT_GPI_REALM)
/* Cover 4TB with L0GTP */
#define PLATFORM_GPCCR_PPS GPCCR_PPS_4TB
#define PLAT_QEMU_GPCCR_PPS GPCCR_PPS_4TB
#define PLAT_QEMU_PPS SZ_4T
/* GPT Configuration options */
#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS