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https://github.com/ARM-software/arm-trusted-firmware.git
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e0ae9fab61
This patch introduces some assembler macros to simplify the declaration of the exception vectors. It abstracts the section the exception code is put into as well as the alignments constraints mandated by the ARMv8 architecture. For all TF images, the exception code has been updated to make use of these macros. This patch also updates some invalid comments in the exception vector code. Change-Id: I35737b8f1c8c24b6da89b0a954c8152a4096fa95
233 lines
6.1 KiB
ArmAsm
233 lines
6.1 KiB
ArmAsm
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ASM_MACROS_S__
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#define __ASM_MACROS_S__
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#include <arch.h>
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.macro func_prologue
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stp x29, x30, [sp, #-0x10]!
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mov x29,sp
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.endm
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.macro func_epilogue
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ldp x29, x30, [sp], #0x10
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.endm
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.macro dcache_line_size reg, tmp
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mrs \tmp, ctr_el0
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ubfx \tmp, \tmp, #16, #4
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro icache_line_size reg, tmp
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mrs \tmp, ctr_el0
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and \tmp, \tmp, #0xf
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro smc_check label
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mrs x0, esr_el3
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ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x0, #EC_AARCH64_SMC
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b.ne $label
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.endm
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 2KB boundary, as required by the ARMv8 architecture.
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*/
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.macro vector_base label
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.section .vectors, "ax"
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.align 11
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\label:
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.endm
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/*
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* Create an entry in the exception vector table, enforcing it is
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* aligned on a 128-byte boundary, as required by the ARMv8 architecture.
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*/
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.macro vector_entry label
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.section .vectors, "ax"
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.align 7
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\label:
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.endm
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/*
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* This macro verifies that the given vector doesn't exceed the
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* architectural limit of 32 instructions. This is meant to be placed
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* immediately after the last instruction in the vector. It takes the
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* vector entry as the parameter
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*/
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.macro check_vector_size since
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.if (. - \since) > (32 * 4)
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.error "Vector exceeds 32 instructions"
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.endif
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.endm
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/*
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* This macro is used to create a function label and place the
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* code into a separate text section based on the function name
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* to enable elimination of unused code during linking
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*/
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.macro func _name
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.section .text.\_name, "ax"
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.type \_name, %function
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.func \_name
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\_name:
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.endm
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/*
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* This macro is used to mark the end of a function.
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*/
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.macro endfunc _name
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.endfunc
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.size \_name, . - \_name
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.endm
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/*
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* Theses macros are used to create function labels for deprecated
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* APIs. If ERROR_DEPRECATED is non zero, the callers of these APIs
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* will fail to link and cause build failure.
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*/
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#if ERROR_DEPRECATED
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.macro func_deprecated _name
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func deprecated\_name
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.endm
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.macro endfunc_deprecated _name
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endfunc deprecated\_name
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.endm
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#else
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.macro func_deprecated _name
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func \_name
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.endm
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.macro endfunc_deprecated _name
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endfunc \_name
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.endm
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#endif
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/*
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* This macro declares an array of 1 or more stacks, properly
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* aligned and in the requested section
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*/
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#define STACK_ALIGN 6
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.macro declare_stack _name, _section, _size, _count
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.if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0)
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.error "Stack size not correctly aligned"
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.endif
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.section \_section, "aw", %nobits
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.align STACK_ALIGN
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\_name:
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.space ((\_count) * (\_size)), 0
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.endm
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#if ENABLE_PLAT_COMPAT
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/*
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* This macro calculates the base address of an MP stack using the
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* platform_get_core_pos() index, the name of the stack storage and
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* the size of each stack
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* In: X0 = MPIDR of CPU whose stack is wanted
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* Out: X0 = physical address of stack base
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* Clobber: X30, X1, X2
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*/
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.macro get_mp_stack _name, _size
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bl platform_get_core_pos
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ldr x2, =(\_name + \_size)
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mov x1, #\_size
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madd x0, x0, x1, x2
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.endm
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#endif
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/*
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* This macro calculates the base address of the current CPU's MP stack
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* using the plat_my_core_pos() index, the name of the stack storage
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* and the size of each stack
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* Out: X0 = physical address of stack base
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* Clobber: X30, X1, X2
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*/
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.macro get_my_mp_stack _name, _size
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bl plat_my_core_pos
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ldr x2, =(\_name + \_size)
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mov x1, #\_size
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madd x0, x0, x1, x2
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.endm
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/*
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* This macro calculates the base address of a UP stack using the
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* name of the stack storage and the size of the stack
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* Out: X0 = physical address of stack base
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*/
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.macro get_up_stack _name, _size
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ldr x0, =(\_name + \_size)
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.endm
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/*
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* Helper macro to generate the best mov/movk combinations according
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* the value to be moved. The 16 bits from '_shift' are tested and
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* if not zero, they are moved into '_reg' without affecting
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* other bits.
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*/
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.macro _mov_imm16 _reg, _val, _shift
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.if (\_val >> \_shift) & 0xffff
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.if (\_val & (1 << \_shift - 1))
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movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
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.else
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mov \_reg, \_val & (0xffff << \_shift)
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.endif
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.endif
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.endm
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/*
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* Helper macro to load arbitrary values into 32 or 64-bit registers
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* which generates the best mov/movk combinations. Many base addresses
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* are 64KB aligned the macro will eliminate updating bits 15:0 in
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* that case
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*/
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.macro mov_imm _reg, _val
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.if (\_val) == 0
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mov \_reg, #0
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.else
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_mov_imm16 \_reg, (\_val), 0
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_mov_imm16 \_reg, (\_val), 16
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_mov_imm16 \_reg, (\_val), 32
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_mov_imm16 \_reg, (\_val), 48
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.endif
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.endm
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#endif /* __ASM_MACROS_S__ */
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