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Introduce some helper macros for exception vectors
This patch introduces some assembler macros to simplify the declaration of the exception vectors. It abstracts the section the exception code is put into as well as the alignments constraints mandated by the ARMv8 architecture. For all TF images, the exception code has been updated to make use of these macros. This patch also updates some invalid comments in the exception vector code. Change-Id: I35737b8f1c8c24b6da89b0a954c8152a4096fa95
This commit is contained in:
Sandrine Bailleux
parent
e141aa0357
commit
e0ae9fab61
5 changed files with 116 additions and 165 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -34,42 +34,37 @@
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#include <bl1.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL1.
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* -----------------------------------------------------------------------------
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*/
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.globl bl1_exceptions
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.section .vectors, "ax"; .align 11
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vector_base bl1_exceptions
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/* -----------------------------------------------------
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* Very simple stackless exception handlers used by BL1.
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* -----------------------------------------------------
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*/
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.align 7
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bl1_exceptions:
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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SynchronousExceptionSP0:
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vector_entry SynchronousExceptionSP0
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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b SynchronousExceptionSP0
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check_vector_size SynchronousExceptionSP0
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.align 7
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IrqSP0:
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vector_entry IrqSP0
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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b IrqSP0
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check_vector_size IrqSP0
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.align 7
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FiqSP0:
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vector_entry FiqSP0
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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b FiqSP0
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check_vector_size FiqSP0
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.align 7
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SErrorSP0:
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vector_entry SErrorSP0
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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b SErrorSP0
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@ -79,29 +74,25 @@ SErrorSP0:
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionSPx:
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vector_entry SynchronousExceptionSPx
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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b SynchronousExceptionSPx
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check_vector_size SynchronousExceptionSPx
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.align 7
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IrqSPx:
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vector_entry IrqSPx
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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b IrqSPx
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check_vector_size IrqSPx
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.align 7
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FiqSPx:
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vector_entry FiqSPx
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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b FiqSPx
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check_vector_size FiqSPx
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.align 7
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SErrorSPx:
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vector_entry SErrorSPx
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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b SErrorSPx
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@ -111,8 +102,7 @@ SErrorSPx:
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionA64:
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vector_entry SynchronousExceptionA64
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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@ -127,22 +117,19 @@ SynchronousExceptionA64:
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b smc_handler64
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check_vector_size SynchronousExceptionA64
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.align 7
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IrqA64:
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vector_entry IrqA64
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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b IrqA64
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check_vector_size IrqA64
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.align 7
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FiqA64:
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vector_entry FiqA64
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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b FiqA64
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check_vector_size FiqA64
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.align 7
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SErrorA64:
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vector_entry SErrorA64
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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b SErrorA64
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@ -152,29 +139,25 @@ SErrorA64:
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionA32:
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vector_entry SynchronousExceptionA32
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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b SynchronousExceptionA32
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check_vector_size SynchronousExceptionA32
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.align 7
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IrqA32:
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vector_entry IrqA32
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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b IrqA32
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check_vector_size IrqA32
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.align 7
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FiqA32:
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vector_entry FiqA32
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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b FiqA32
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check_vector_size FiqA32
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.align 7
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SErrorA32:
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vector_entry SErrorA32
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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b SErrorA32
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -161,14 +161,14 @@ interrupt_exit_\label:
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str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
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.endm
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.section .vectors, "ax"; .align 11
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.align 7
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runtime_exceptions:
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vector_base runtime_exceptions
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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sync_exception_sp_el0:
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vector_entry sync_exception_sp_el0
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/* -----------------------------------------------------
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* We don't expect any synchronous exceptions from EL3
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* -----------------------------------------------------
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@ -176,23 +176,22 @@ sync_exception_sp_el0:
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bl report_unhandled_exception
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check_vector_size sync_exception_sp_el0
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.align 7
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/* -----------------------------------------------------
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* EL3 code is non-reentrant. Any asynchronous exception
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* is a serious error. Loop infinitely.
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* -----------------------------------------------------
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*/
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irq_sp_el0:
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vector_entry irq_sp_el0
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bl report_unhandled_interrupt
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check_vector_size irq_sp_el0
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.align 7
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fiq_sp_el0:
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vector_entry fiq_sp_el0
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bl report_unhandled_interrupt
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check_vector_size fiq_sp_el0
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.align 7
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serror_sp_el0:
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vector_entry serror_sp_el0
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bl report_unhandled_exception
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check_vector_size serror_sp_el0
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@ -200,8 +199,8 @@ serror_sp_el0:
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_sp_elx:
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vector_entry sync_exception_sp_elx
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/* -----------------------------------------------------
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* This exception will trigger if anything went wrong
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* during a previous exception entry or exit or while
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@ -212,18 +211,15 @@ sync_exception_sp_elx:
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bl report_unhandled_exception
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check_vector_size sync_exception_sp_elx
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.align 7
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irq_sp_elx:
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vector_entry irq_sp_elx
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bl report_unhandled_interrupt
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check_vector_size irq_sp_elx
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.align 7
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fiq_sp_elx:
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vector_entry fiq_sp_elx
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bl report_unhandled_interrupt
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check_vector_size fiq_sp_elx
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.align 7
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serror_sp_elx:
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vector_entry serror_sp_elx
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bl report_unhandled_exception
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check_vector_size serror_sp_elx
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@ -231,8 +227,7 @@ serror_sp_elx:
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch64:
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vector_entry sync_exception_aarch64
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/* -----------------------------------------------------
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* This exception vector will be the entry point for
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* SMCs and traps that are unhandled at lower ELs most
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@ -244,23 +239,20 @@ sync_exception_aarch64:
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handle_sync_exception
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check_vector_size sync_exception_aarch64
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.align 7
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/* -----------------------------------------------------
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* Asynchronous exceptions from lower ELs are not
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* currently supported. Report their occurrence.
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* -----------------------------------------------------
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*/
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irq_aarch64:
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vector_entry irq_aarch64
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handle_interrupt_exception irq_aarch64
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check_vector_size irq_aarch64
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.align 7
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fiq_aarch64:
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vector_entry fiq_aarch64
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handle_interrupt_exception fiq_aarch64
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check_vector_size fiq_aarch64
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.align 7
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serror_aarch64:
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vector_entry serror_aarch64
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bl report_unhandled_exception
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check_vector_size serror_aarch64
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@ -268,8 +260,7 @@ serror_aarch64:
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch32:
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vector_entry sync_exception_aarch32
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/* -----------------------------------------------------
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* This exception vector will be the entry point for
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* SMCs and traps that are unhandled at lower ELs most
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@ -281,27 +272,23 @@ sync_exception_aarch32:
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handle_sync_exception
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check_vector_size sync_exception_aarch32
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.align 7
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/* -----------------------------------------------------
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* Asynchronous exceptions from lower ELs are not
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* currently supported. Report their occurrence.
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* -----------------------------------------------------
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*/
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irq_aarch32:
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vector_entry irq_aarch32
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handle_interrupt_exception irq_aarch32
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check_vector_size irq_aarch32
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.align 7
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fiq_aarch32:
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vector_entry fiq_aarch32
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handle_interrupt_exception fiq_aarch32
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check_vector_size fiq_aarch32
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.align 7
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serror_aarch32:
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vector_entry serror_aarch32
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bl report_unhandled_exception
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check_vector_size serror_aarch32
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.align 7
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/* -----------------------------------------------------
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* The following code handles secure monitor calls.
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@ -28,10 +28,10 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bl_common.h>
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#include <arch.h>
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#include <tsp.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <tsp.h>
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/* ----------------------------------------------------
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@ -98,110 +98,90 @@ interrupt_exit_\label:
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* TSP exception handlers.
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* -----------------------------------------------------
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*/
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.section .vectors, "ax"; .align 11
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.align 7
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tsp_exceptions:
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vector_base tsp_exceptions
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x180. No exceptions
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* Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
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* are expected and treated as irrecoverable errors.
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* -----------------------------------------------------
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*/
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sync_exception_sp_el0:
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vector_entry sync_exception_sp_el0
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bl plat_panic_handler
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check_vector_size sync_exception_sp_el0
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.align 7
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irq_sp_el0:
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vector_entry irq_sp_el0
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bl plat_panic_handler
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check_vector_size irq_sp_el0
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.align 7
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fiq_sp_el0:
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vector_entry fiq_sp_el0
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bl plat_panic_handler
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check_vector_size fiq_sp_el0
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.align 7
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serror_sp_el0:
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vector_entry serror_sp_el0
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bl plat_panic_handler
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check_vector_size serror_sp_el0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x380. Only IRQs/FIQs
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* Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
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* are expected and handled
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_sp_elx:
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vector_entry sync_exception_sp_elx
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bl plat_panic_handler
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check_vector_size sync_exception_sp_elx
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.align 7
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irq_sp_elx:
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vector_entry irq_sp_elx
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handle_tsp_interrupt irq_sp_elx
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check_vector_size irq_sp_elx
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.align 7
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fiq_sp_elx:
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vector_entry fiq_sp_elx
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handle_tsp_interrupt fiq_sp_elx
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check_vector_size fiq_sp_elx
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.align 7
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serror_sp_elx:
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vector_entry serror_sp_elx
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bl plat_panic_handler
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check_vector_size serror_sp_elx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x580. No exceptions
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* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
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* are handled since TSP does not implement a lower EL
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch64:
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vector_entry sync_exception_aarch64
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bl plat_panic_handler
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check_vector_size sync_exception_aarch64
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.align 7
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irq_aarch64:
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vector_entry irq_aarch64
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bl plat_panic_handler
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check_vector_size irq_aarch64
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.align 7
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fiq_aarch64:
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vector_entry fiq_aarch64
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bl plat_panic_handler
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check_vector_size fiq_aarch64
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.align 7
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serror_aarch64:
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vector_entry serror_aarch64
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bl plat_panic_handler
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check_vector_size serror_aarch64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x780. No exceptions
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* Lower EL using AArch32 : 0x600 - 0x800. No exceptions
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* handled since the TSP does not implement a lower EL.
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch32:
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vector_entry sync_exception_aarch32
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bl plat_panic_handler
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check_vector_size sync_exception_aarch32
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.align 7
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irq_aarch32:
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vector_entry irq_aarch32
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bl plat_panic_handler
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check_vector_size irq_aarch32
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.align 7
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fiq_aarch32:
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vector_entry fiq_aarch32
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bl plat_panic_handler
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check_vector_size fiq_aarch32
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.align 7
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serror_aarch32:
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vector_entry serror_aarch32
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bl plat_panic_handler
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check_vector_size serror_aarch32
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.align 7
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -31,140 +31,122 @@
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#include <asm_macros.S>
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#include <bl_common.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL2 and BL31 stages.
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* BL31 uses them before stacks are setup. BL2 uses them throughout.
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* -----------------------------------------------------------------------------
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*/
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.globl early_exceptions
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.section .vectors, "ax"; .align 11
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vector_base early_exceptions
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/* -----------------------------------------------------
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* Very simple stackless exception handlers used by BL2
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* and BL31 bootloader stages. BL31 uses them before
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* stacks are setup. BL2 uses them throughout.
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
|
||||
*/
|
||||
.align 7
|
||||
early_exceptions:
|
||||
/* -----------------------------------------------------
|
||||
* Current EL with SP0 : 0x0 - 0x180
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
SynchronousExceptionSP0:
|
||||
vector_entry SynchronousExceptionSP0
|
||||
mov x0, #SYNC_EXCEPTION_SP_EL0
|
||||
bl plat_report_exception
|
||||
b SynchronousExceptionSP0
|
||||
check_vector_size SynchronousExceptionSP0
|
||||
|
||||
.align 7
|
||||
IrqSP0:
|
||||
vector_entry IrqSP0
|
||||
mov x0, #IRQ_SP_EL0
|
||||
bl plat_report_exception
|
||||
b IrqSP0
|
||||
check_vector_size IrqSP0
|
||||
|
||||
.align 7
|
||||
FiqSP0:
|
||||
vector_entry FiqSP0
|
||||
mov x0, #FIQ_SP_EL0
|
||||
bl plat_report_exception
|
||||
b FiqSP0
|
||||
check_vector_size FiqSP0
|
||||
|
||||
.align 7
|
||||
SErrorSP0:
|
||||
vector_entry SErrorSP0
|
||||
mov x0, #SERROR_SP_EL0
|
||||
bl plat_report_exception
|
||||
b SErrorSP0
|
||||
check_vector_size SErrorSP0
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Current EL with SPx: 0x200 - 0x380
|
||||
* Current EL with SPx: 0x200 - 0x400
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
.align 7
|
||||
SynchronousExceptionSPx:
|
||||
vector_entry SynchronousExceptionSPx
|
||||
mov x0, #SYNC_EXCEPTION_SP_ELX
|
||||
bl plat_report_exception
|
||||
b SynchronousExceptionSPx
|
||||
check_vector_size SynchronousExceptionSPx
|
||||
|
||||
.align 7
|
||||
IrqSPx:
|
||||
vector_entry IrqSPx
|
||||
mov x0, #IRQ_SP_ELX
|
||||
bl plat_report_exception
|
||||
b IrqSPx
|
||||
check_vector_size IrqSPx
|
||||
|
||||
.align 7
|
||||
FiqSPx:
|
||||
vector_entry FiqSPx
|
||||
mov x0, #FIQ_SP_ELX
|
||||
bl plat_report_exception
|
||||
b FiqSPx
|
||||
check_vector_size FiqSPx
|
||||
|
||||
.align 7
|
||||
SErrorSPx:
|
||||
vector_entry SErrorSPx
|
||||
mov x0, #SERROR_SP_ELX
|
||||
bl plat_report_exception
|
||||
b SErrorSPx
|
||||
check_vector_size SErrorSPx
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Lower EL using AArch64 : 0x400 - 0x580
|
||||
* Lower EL using AArch64 : 0x400 - 0x600
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
.align 7
|
||||
SynchronousExceptionA64:
|
||||
vector_entry SynchronousExceptionA64
|
||||
mov x0, #SYNC_EXCEPTION_AARCH64
|
||||
bl plat_report_exception
|
||||
b SynchronousExceptionA64
|
||||
check_vector_size SynchronousExceptionA64
|
||||
|
||||
.align 7
|
||||
IrqA64:
|
||||
vector_entry IrqA64
|
||||
mov x0, #IRQ_AARCH64
|
||||
bl plat_report_exception
|
||||
b IrqA64
|
||||
check_vector_size IrqA64
|
||||
|
||||
.align 7
|
||||
FiqA64:
|
||||
vector_entry FiqA64
|
||||
mov x0, #FIQ_AARCH64
|
||||
bl plat_report_exception
|
||||
b FiqA64
|
||||
check_vector_size FiqA64
|
||||
|
||||
.align 7
|
||||
SErrorA64:
|
||||
vector_entry SErrorA64
|
||||
mov x0, #SERROR_AARCH64
|
||||
bl plat_report_exception
|
||||
b SErrorA64
|
||||
check_vector_size SErrorA64
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Lower EL using AArch32 : 0x0 - 0x180
|
||||
* Lower EL using AArch32 : 0x600 - 0x800
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
.align 7
|
||||
SynchronousExceptionA32:
|
||||
vector_entry SynchronousExceptionA32
|
||||
mov x0, #SYNC_EXCEPTION_AARCH32
|
||||
bl plat_report_exception
|
||||
b SynchronousExceptionA32
|
||||
check_vector_size SynchronousExceptionA32
|
||||
|
||||
.align 7
|
||||
IrqA32:
|
||||
vector_entry IrqA32
|
||||
mov x0, #IRQ_AARCH32
|
||||
bl plat_report_exception
|
||||
b IrqA32
|
||||
check_vector_size IrqA32
|
||||
|
||||
.align 7
|
||||
FiqA32:
|
||||
vector_entry FiqA32
|
||||
mov x0, #FIQ_AARCH32
|
||||
bl plat_report_exception
|
||||
b FiqA32
|
||||
check_vector_size FiqA32
|
||||
|
||||
.align 7
|
||||
SErrorA32:
|
||||
vector_entry SErrorA32
|
||||
mov x0, #SERROR_AARCH32
|
||||
bl plat_report_exception
|
||||
b SErrorA32
|
||||
|
|
|
|||
|
|
@ -66,11 +66,30 @@
|
|||
b.ne $label
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Declare the exception vector table, enforcing it is aligned on a
|
||||
* 2KB boundary, as required by the ARMv8 architecture.
|
||||
*/
|
||||
.macro vector_base label
|
||||
.section .vectors, "ax"
|
||||
.align 11
|
||||
\label:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This macro verifies that the a given vector doesn't exceed the
|
||||
* Create an entry in the exception vector table, enforcing it is
|
||||
* aligned on a 128-byte boundary, as required by the ARMv8 architecture.
|
||||
*/
|
||||
.macro vector_entry label
|
||||
.section .vectors, "ax"
|
||||
.align 7
|
||||
\label:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This macro verifies that the given vector doesn't exceed the
|
||||
* architectural limit of 32 instructions. This is meant to be placed
|
||||
* immedately after the last instruction in the vector. It takes the
|
||||
* immediately after the last instruction in the vector. It takes the
|
||||
* vector entry as the parameter
|
||||
*/
|
||||
.macro check_vector_size since
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue