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6a6b282378
Cortex-A715 erratum 2561034 is a Cat B erratum that applies to revision r1p0 and is fixed in r1p1. The workaround is to set bit[26] in CPUACTLR2_EL1. Setting this bit is not expected to have a significant performance impact. SDEN documentation: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: I377f250a2994b6ced3ac7d93f947af6ceb690d49 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
31 lines
1.2 KiB
C
31 lines
1.2 KiB
C
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A715_H
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#define CORTEX_A715_H
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#define CORTEX_A715_MIDR U(0x410FD4D0)
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/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A715_BHB_LOOP_COUNT U(38)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_A715_H */
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