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https://github.com/ARM-software/arm-trusted-firmware.git
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673406b508
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I51278beacbe6da79853c3f0f0f94cd806fc9652c Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
114 lines
2.4 KiB
C
114 lines
2.4 KiB
C
/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include "ulcb_cpld.h"
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#define SCLK 8 /* GP_6_8 */
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#define SSTBZ 3 /* GP_2_3 */
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#define MOSI 7 /* GP_6_7 */
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#define CPLD_ADDR_RESET 0x80 /* RW */
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/* LSI Multiplexed Pin Setting Mask Register */
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#define PFC_PMMR 0xE6060000
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/* General output registers */
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#define GPIO_OUTDT2 0xE6052008
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#define GPIO_OUTDT6 0xE6055408
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/* General input/output switching registers */
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#define GPIO_INOUTSEL2 0xE6052004
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#define GPIO_INOUTSEL6 0xE6055404
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/* General IO/Interrupt Switching Register */
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#define GPIO_IOINTSEL6 0xE6055400
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/* GPIO/perihperal function select */
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#define PFC_GPSR2 0xE6060108
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#define PFC_GPSR6 0xE6060118
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static void gpio_set_value(uint32_t addr, uint8_t gpio, uint32_t val)
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{
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uint32_t reg;
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reg = mmio_read_32(addr);
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if (val)
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reg |= (1 << gpio);
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else
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reg &= ~(1 << gpio);
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mmio_write_32(addr, reg);
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}
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static void gpio_direction_output(uint32_t addr, uint8_t gpio)
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{
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uint32_t reg;
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reg = mmio_read_32(addr);
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reg |= (1 << gpio);
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mmio_write_32(addr, reg);
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}
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static void gpio_pfc(uint32_t addr, uint8_t gpio)
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{
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uint32_t reg;
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reg = mmio_read_32(addr);
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reg &= ~(1 << gpio);
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mmio_write_32(PFC_PMMR, ~reg);
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mmio_write_32(addr, reg);
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}
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static void cpld_write(uint8_t addr, uint32_t data)
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{
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int i;
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for (i = 0; i < 32; i++) {
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/* MSB first */
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gpio_set_value(GPIO_OUTDT6, MOSI, data & (1U << 31));
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gpio_set_value(GPIO_OUTDT6, SCLK, 1);
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data <<= 1;
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gpio_set_value(GPIO_OUTDT6, SCLK, 0);
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}
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for (i = 0; i < 8; i++) {
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/* MSB first */
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gpio_set_value(GPIO_OUTDT6, MOSI, addr & 0x80);
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gpio_set_value(GPIO_OUTDT6, SCLK, 1);
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addr <<= 1;
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gpio_set_value(GPIO_OUTDT6, SCLK, 0);
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}
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/* WRITE */
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gpio_set_value(GPIO_OUTDT6, MOSI, 1);
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gpio_set_value(GPIO_OUTDT2, SSTBZ, 0);
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gpio_set_value(GPIO_OUTDT6, SCLK, 1);
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gpio_set_value(GPIO_OUTDT6, SCLK, 0);
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gpio_set_value(GPIO_OUTDT2, SSTBZ, 1);
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}
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static void cpld_init(void)
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{
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gpio_pfc(PFC_GPSR6, SCLK);
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gpio_pfc(PFC_GPSR2, SSTBZ);
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gpio_pfc(PFC_GPSR6, MOSI);
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gpio_set_value(GPIO_IOINTSEL6, SCLK, 0);
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gpio_set_value(GPIO_OUTDT6, SCLK, 0);
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gpio_set_value(GPIO_OUTDT2, SSTBZ, 1);
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gpio_set_value(GPIO_OUTDT6, MOSI, 0);
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gpio_direction_output(GPIO_INOUTSEL6, SCLK);
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gpio_direction_output(GPIO_INOUTSEL2, SSTBZ);
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gpio_direction_output(GPIO_INOUTSEL6, MOSI);
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}
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void rcar_cpld_reset_cpu(void)
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{
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cpld_init();
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cpld_write(CPLD_ADDR_RESET, 1);
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}
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