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0ad5b318f7
DynamIQ based designs have upto 8 CPUs in each cluster. This patch fixes the device tree node which describes the topology of the CPU for DynamIQ FVP Model. Change-Id: I7146bc79029ce38314026d4853e5b6406863725c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
40 lines
537 B
Text
40 lines
537 B
Text
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include "fvp-base-gicv3-psci-common.dtsi"
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/* DynamIQ based designs have upto 8 CPUs in each cluster */
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&CPU_MAP {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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