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Fix topology description of cpus for DynamIQ based FVP

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DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.

Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This commit is contained in:
Madhukar Pappireddy 2020-02-13 15:36:50 -06:00
parent 572fcdd547
commit 0ad5b318f7
4 changed files with 43 additions and 3 deletions
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2
fdts/fvp-base-gicv3-psci-common.dtsi
View file

@ -39,7 +39,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
CPU_MAP:cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;

2
fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include "fvp-base-gicv3-psci-common.dtsi"
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 {
reg = <0x0 0x0>;

40
fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi Normal file
View file

@ -0,0 +1,40 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include "fvp-base-gicv3-psci-common.dtsi"
/* DynamIQ based designs have upto 8 CPUs in each cluster */
&CPU_MAP {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};

2
fdts/fvp-base-gicv3-psci-dynamiq.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include "fvp-base-gicv3-psci-common.dtsi"
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 {
reg = <0x0 0x0>;