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arm-trusted-firmware/plat/intel/soc/agilex/include
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Sieu Mun Tang ce21a1a909 feat(intel): update Agilex5 DDR and IOSSM driver 
DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
2024-10-07 17:28:30 +02:00
..
agilex_clock_manager.h fix(intel): fix hardcoded mpu frequency ticks 2023-12-18 10:12:29 +08:00
agilex_memory_controller.h feat(intel): restructure sys mgr for Agilex 2023-05-23 21:13:05 +08:00
agilex_mmc.h plat: intel: set DRVSEL and SMPLSEL for DWMMC 2020-06-08 22:03:34 +00:00
agilex_pinmux.h feat(intel): setup FPGA interface for Agilex 2022-11-22 23:35:36 +08:00
agilex_system_manager.h feat(intel): support QSPI ECC Linux for Agilex 2023-12-22 00:44:35 +08:00
socfpga_plat_def.h feat(intel): update Agilex5 DDR and IOSSM driver 2024-10-07 17:28:30 +02:00