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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
254 lines
8.1 KiB
C
254 lines
8.1 KiB
C
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <bl32/tsp/tsp.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include "tspd_private.h"
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/*******************************************************************************
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* The target cpu is being turned on. Allow the TSPD/TSP to perform any actions
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* needed. Nothing at the moment.
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******************************************************************************/
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static void tspd_cpu_on_handler(u_register_t target_cpu)
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{
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}
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/*******************************************************************************
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* This cpu is being turned off. Allow the TSPD/TSP to perform any actions
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* needed
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******************************************************************************/
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static int32_t tspd_cpu_off_handler(u_register_t unused)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
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/*
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* Abort any preempted SMC request before overwriting the SECURE
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* context.
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*/
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tspd_abort_preempted_smc(tsp_ctx);
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/* Program the entry point and enter the TSP */
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cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry);
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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/*
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* Read the response from the TSP. A non-zero return means that
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* something went wrong while communicating with the TSP.
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*/
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if (rc != 0)
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panic();
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/*
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* Reset TSP's context for a fresh start when this cpu is turned on
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* subsequently.
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*/
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set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF);
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return 0;
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}
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/*******************************************************************************
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* This cpu is being suspended. S-EL1 state must have been saved in the
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* resident cpu (mpidr format) if it is a UP/UP migratable TSP.
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******************************************************************************/
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static void tspd_cpu_suspend_handler(u_register_t max_off_pwrlvl)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
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/*
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* Abort any preempted SMC request before overwriting the SECURE
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* context.
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*/
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tspd_abort_preempted_smc(tsp_ctx);
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/* Program the entry point and enter the TSP */
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cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry);
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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/*
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* Read the response from the TSP. A non-zero return means that
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* something went wrong while communicating with the TSP.
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*/
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if (rc)
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panic();
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/* Update its context to reflect the state the TSP is in */
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set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND);
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}
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/*******************************************************************************
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* This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits
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* before passing control back to the Secure Monitor. Entry in S-EL1 is done
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* after initialising minimal architectural state that guarantees safe
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* execution.
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******************************************************************************/
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static void tspd_cpu_on_finish_handler(u_register_t unused)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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entry_point_info_t tsp_on_entrypoint;
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF);
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tspd_init_tsp_ep_state(&tsp_on_entrypoint,
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TSP_AARCH64,
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(uint64_t) &tsp_vectors->cpu_on_entry,
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tsp_ctx);
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/* Initialise this cpu's secure context */
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cm_init_my_context(&tsp_on_entrypoint);
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#if TSP_NS_INTR_ASYNC_PREEMPT
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/*
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* Disable the NS interrupt locally since it will be enabled globally
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* within cm_init_my_context.
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*/
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disable_intr_rm_local(INTR_TYPE_NS, SECURE);
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#endif
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/* Enter the TSP */
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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/*
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* Read the response from the TSP. A non-zero return means that
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* something went wrong while communicating with the SP.
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*/
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if (rc != 0)
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panic();
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/* Update its context to reflect the state the SP is in */
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set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
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}
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/*******************************************************************************
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* This cpu has resumed from suspend. The SPD saved the TSP context when it
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* completed the preceding suspend call. Use that context to program an entry
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* into the TSP to allow it to do any remaining book keeping
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******************************************************************************/
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static void tspd_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND);
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/* Program the entry point, max_off_pwrlvl and enter the SP */
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write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
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CTX_GPREG_X0,
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max_off_pwrlvl);
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cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry);
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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/*
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* Read the response from the TSP. A non-zero return means that
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* something went wrong while communicating with the TSP.
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*/
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if (rc != 0)
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panic();
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/* Update its context to reflect the state the SP is in */
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set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
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}
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/*******************************************************************************
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* Return the type of TSP the TSPD is dealing with. Report the current resident
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* cpu (mpidr format) if it is a UP/UP migratable TSP.
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******************************************************************************/
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static int32_t tspd_cpu_migrate_info(u_register_t *resident_cpu)
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{
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return TSP_MIGRATE_INFO;
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}
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/*******************************************************************************
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* System is about to be switched off. Allow the TSPD/TSP to perform
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* any actions needed.
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******************************************************************************/
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static void tspd_system_off(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
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/*
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* Abort any preempted SMC request before overwriting the SECURE
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* context.
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*/
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tspd_abort_preempted_smc(tsp_ctx);
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/* Program the entry point */
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cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry);
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/* Enter the TSP. We do not care about the return value because we
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* must continue the shutdown anyway */
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tspd_synchronous_sp_entry(tsp_ctx);
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}
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/*******************************************************************************
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* System is about to be reset. Allow the TSPD/TSP to perform
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* any actions needed.
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******************************************************************************/
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static void tspd_system_reset(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
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/*
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* Abort any preempted SMC request before overwriting the SECURE
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* context.
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*/
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tspd_abort_preempted_smc(tsp_ctx);
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/* Program the entry point */
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cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry);
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/*
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* Enter the TSP. We do not care about the return value because we
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* must continue the reset anyway
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*/
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tspd_synchronous_sp_entry(tsp_ctx);
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}
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/*******************************************************************************
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* Structure populated by the TSP Dispatcher to be given a chance to perform any
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* TSP bookkeeping before PSCI executes a power mgmt. operation.
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******************************************************************************/
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const spd_pm_ops_t tspd_pm = {
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.svc_on = tspd_cpu_on_handler,
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.svc_off = tspd_cpu_off_handler,
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.svc_suspend = tspd_cpu_suspend_handler,
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.svc_on_finish = tspd_cpu_on_finish_handler,
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.svc_suspend_finish = tspd_cpu_suspend_finish_handler,
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.svc_migrate = NULL,
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.svc_migrate_info = tspd_cpu_migrate_info,
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.svc_system_off = tspd_system_off,
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.svc_system_reset = tspd_system_reset
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};
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