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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <bl32/tsp/tsp.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/utils.h>
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#include "tspd_private.h"
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/*******************************************************************************
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* Given a secure payload entrypoint info pointer, entry point PC, register
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* width, cpu id & pointer to a context data structure, this function will
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* initialize tsp context and entry point info for the secure payload
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******************************************************************************/
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void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point,
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uint32_t rw,
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uint64_t pc,
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tsp_context_t *tsp_ctx)
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{
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uint32_t ep_attr;
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/* Passing a NULL context is a critical programming error */
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assert(tsp_ctx);
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assert(tsp_entry_point);
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assert(pc);
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/*
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* We support AArch64 TSP for now.
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* TODO: Add support for AArch32 TSP
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*/
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assert(rw == TSP_AARCH64);
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/* Associate this context with the cpu specified */
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tsp_ctx->mpidr = read_mpidr_el1();
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tsp_ctx->state = 0;
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set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF);
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clr_yield_smc_active_flag(tsp_ctx->state);
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cm_set_context(&tsp_ctx->cpu_ctx, SECURE);
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/* initialise an entrypoint to set up the CPU context */
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ep_attr = SECURE | EP_ST_ENABLE;
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if (read_sctlr_el3() & SCTLR_EE_BIT)
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ep_attr |= EP_EE_BIG;
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SET_PARAM_HEAD(tsp_entry_point, PARAM_EP, VERSION_1, ep_attr);
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tsp_entry_point->pc = pc;
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tsp_entry_point->spsr = SPSR_64(MODE_EL1,
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MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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zeromem(&tsp_entry_point->args, sizeof(tsp_entry_point->args));
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}
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/*******************************************************************************
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* This function takes an SP context pointer and:
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* 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx.
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* 2. Saves the current C runtime state (callee saved registers) on the stack
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* frame and saves a reference to this state.
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* 3. Calls el3_exit() so that the EL3 system and general purpose registers
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* from the tsp_ctx->cpu_ctx are used to enter the secure payload image.
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******************************************************************************/
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uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx)
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{
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uint64_t rc;
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assert(tsp_ctx != NULL);
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assert(tsp_ctx->c_rt_ctx == 0);
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/* Apply the Secure EL1 system register context and switch to it */
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assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
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cm_el1_sysregs_context_restore(SECURE);
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cm_set_next_eret_context(SECURE);
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rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx);
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#if ENABLE_ASSERTIONS
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tsp_ctx->c_rt_ctx = 0;
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#endif
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return rc;
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}
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/*******************************************************************************
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* This function takes an SP context pointer and:
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* 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx.
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* 2. Restores the current C runtime state (callee saved registers) from the
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* stack frame using the reference to this state saved in tspd_enter_sp().
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* 3. It does not need to save any general purpose or EL3 system register state
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* as the generic smc entry routine should have saved those.
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******************************************************************************/
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void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret)
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{
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assert(tsp_ctx != NULL);
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/* Save the Secure EL1 system register context */
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assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
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cm_el1_sysregs_context_save(SECURE);
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assert(tsp_ctx->c_rt_ctx != 0);
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tspd_exit_sp(tsp_ctx->c_rt_ctx, ret);
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/* Should never reach here */
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assert(0);
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}
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/*******************************************************************************
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* This function takes an SP context pointer and abort any preempted SMC
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* request.
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* Return 1 if there was a preempted SMC request, 0 otherwise.
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******************************************************************************/
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int tspd_abort_preempted_smc(tsp_context_t *tsp_ctx)
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{
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if (!get_yield_smc_active_flag(tsp_ctx->state))
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return 0;
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/* Abort any preempted SMC request */
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clr_yield_smc_active_flag(tsp_ctx->state);
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/*
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* Arrange for an entry into the test secure payload. It will
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* be returned via TSP_ABORT_DONE case in tspd_smc_handler.
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*/
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cm_set_elr_el3(SECURE,
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(uint64_t) &tsp_vectors->abort_yield_smc_entry);
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uint64_t rc = tspd_synchronous_sp_entry(tsp_ctx);
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if (rc != 0)
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panic();
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return 1;
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}
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