Maheedhar Bollapalli df44616a12 fix(zynqmp): handle invalid entry point in cpu hotplug scenario ... Invalid addresses are from 2G-4G and also address where TF-A is. Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>		2025-03-26 06:33:09 +00:00
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aarch64	Merge changes from topic "xlnx_fix_plat_single_ret" into integration	2025-01-23 11:22:47 +01:00
include	fix(zynqmp): handle invalid entry point in cpu hotplug scenario	2025-03-26 06:33:09 +00:00
pm_service	feat(zynqmp): add pin group for lower qspi interface	2025-03-04 04:06:37 -08:00
tsp	refactor(xilinx): add generic TSP makefile	2023-11-02 10:11:20 +05:30
bl31_zynqmp_setup.c	fix(xilinx): dcc console tests failing	2025-01-21 19:02:51 +05:30
custom_sip_svc.c	fix(zynqmp): add external declaration	2024-11-05 08:10:10 +00:00
libpm.mk	refactor(xilinx): move versal files to common place	2023-03-27 22:57:00 -07:00
plat_psci.c	fix(zynqmp): handle invalid entry point in cpu hotplug scenario	2025-03-26 06:33:09 +00:00
plat_topology.c	fix(zynqmp): add external declaration	2024-11-05 08:10:10 +00:00
plat_zynqmp.c	fix(zynqmp): modify function to have single return	2025-01-15 05:46:12 +00:00
platform.mk	feat(xilinx): add none console	2024-10-14 08:39:15 +00:00
sip_svc_setup.c	fix(zynqmp): modify conditions to have boolean type	2024-10-30 07:05:30 +00:00
zynqmp_ehf.c	chore(xilinx): reorder include files as per TF-A guidelines	2023-06-27 10:14:09 +05:30
zynqmp_ipi.c	chore(xilinx): follow kernel doc format for functional documentation	2023-06-23 08:07:13 +01:00
zynqmp_sdei.c	chore(xilinx): reorder include files as per TF-A guidelines	2023-06-27 10:14:09 +05:30