Jit Loon Lim 646a9a1615 fix(intel): update warm reset routine and bootscratch register usage ... Agilex5 platform: Boot scratch COLD6 register is meant for Customer use only. So, use Intel specific COLD3 register with [5:2]bits to determine the warm reset and SMP boot requests. Also handle the unaligned DEVICE/IO memory store and load in the assembly entrypoint startup code. Agilex, Stratix10, N5X platforms: Use only the LSB 4bits [3:0] of the boot scratch COLD6 register to detect the warm reset request. Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>		2025-01-13 16:31:42 +08:00
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s10_clock_manager.h	fix(intel): revert back to use L4 clock	2023-12-22 11:39:50 +08:00
s10_memory_controller.h	fix(intel): update outdated code for Linux direct boot	2024-10-16 23:36:49 +02:00
s10_mmc.h	feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC	2022-05-05 23:47:20 +08:00
s10_pinmux.h	intel: Refactor common platform code [1/5]	2019-11-28 12:47:57 +08:00
s10_system_manager.h	fix(intel): correct macro naming	2024-10-24 19:43:11 +08:00
socfpga_plat_def.h	fix(intel): update warm reset routine and bootscratch register usage	2025-01-13 16:31:42 +08:00