Jit Loon Lim 646a9a1615 fix(intel): update warm reset routine and bootscratch register usage ... Agilex5 platform: Boot scratch COLD6 register is meant for Customer use only. So, use Intel specific COLD3 register with [5:2]bits to determine the warm reset and SMP boot requests. Also handle the unaligned DEVICE/IO memory store and load in the assembly entrypoint startup code. Agilex, Stratix10, N5X platforms: Use only the LSB 4bits [3:0] of the boot scratch COLD6 register to detect the warm reset request. Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>		2025-01-13 16:31:42 +08:00
..
n5x_clock_manager.h	fix(intel): update Agilex5 BL2 init flow and other misc changes	2024-10-09 20:04:16 +02:00
n5x_system_manager.h	fix(intel): correct macro naming	2024-10-24 19:43:11 +08:00
socfpga_plat_def.h	fix(intel): update warm reset routine and bootscratch register usage	2025-01-13 16:31:42 +08:00