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https://github.com/ARM-software/arm-trusted-firmware.git
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d1c58d8649
This patch provides ATF build version via SMC call on Agilex7, Agilex5, Stratix10 and N5X platforms. Change-Id: I61af83433fe61f85987f38ffc86380a41cdb5289 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
246 lines
9.1 KiB
C
246 lines
9.1 KiB
C
/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_SIP_SVC_H
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#define SOCFPGA_SIP_SVC_H
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/* SiP status response */
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#define INTEL_SIP_SMC_STATUS_OK 0
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#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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#define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3
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#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_RSU_ERROR 0x7
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#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8
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/* SiP mailbox error code */
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#define GENERIC_RESPONSE_ERROR 0x3FF
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/* SiP V2 command code range */
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#define INTEL_SIP_SMC_CMD_MASK 0xFFFF
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#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400
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#define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF
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/* SiP V2 protocol header */
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#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U
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#define INTEL_SIP_SMC_HEADER_CID_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_CID_OFFSET 4U
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#define INTEL_SIP_SMC_HEADER_VERSION_MASK 0xF
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#define INTEL_SIP_SMC_HEADER_VERSION_OFFSET 60U
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/* SMC SiP service function identifier for version 1 */
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/* FPGA Reconfig */
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#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
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/* FPGA Bitstream Flag */
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#define FLAG_PARTIAL_CONFIG BIT(0)
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#define FLAG_AUTHENTICATION BIT(1)
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#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
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== FLAG_##_type)
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/* Secure Register Access */
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#define INTEL_SIP_SMC_REG_READ 0xC2000007
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#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
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#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
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/* Remote System Update */
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#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
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#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
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#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
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#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
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#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
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#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
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#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
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#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
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#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
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#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
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#define INTEL_SIP_SMC_RSU_GET_DEVICE_INFO 0xC2000016
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/* Hardware monitor */
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#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
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#define INTEL_SIP_SMC_HWMON_READVOLT 0xC2000021
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#define TEMP_CHANNEL_MAX (1 << 15)
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#define VOLT_CHANNEL_MAX (1 << 15)
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/* ECC */
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#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
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/* Generic Command */
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#define INTEL_SIP_SMC_SERVICE_COMPLETED 0xC200001E
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#define INTEL_SIP_SMC_FIRMWARE_VERSION 0xC200001F
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#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
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#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
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#define SERVICE_COMPLETED_MODE_ASYNC 0x00004F4E
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/* Mailbox Command */
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#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200003C
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#define INTEL_SIP_SMC_GET_USERCODE 0xC200003D
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/* FPGA Crypto Services */
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#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER 0xC200005A
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#define INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT 0x4200008F
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#define INTEL_SIP_SMC_FCS_CRYPTION 0x4200005B
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#define INTEL_SIP_SMC_FCS_CRYPTION_EXT 0xC2000090
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#define INTEL_SIP_SMC_FCS_SERVICE_REQUEST 0x4200005C
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#define INTEL_SIP_SMC_FCS_SEND_CERTIFICATE 0x4200005D
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#define INTEL_SIP_SMC_FCS_GET_PROVISION_DATA 0x4200005E
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#define INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH 0xC200005F
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#define INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN 0xC2000064
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#define INTEL_SIP_SMC_FCS_CHIP_ID 0xC2000065
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#define INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY 0xC2000066
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#define INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS 0xC2000067
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#define INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT 0xC2000068
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#define INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD 0xC2000069
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#define INTEL_SIP_SMC_FCS_OPEN_CS_SESSION 0xC200006E
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#define INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION 0xC200006F
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#define INTEL_SIP_SMC_FCS_IMPORT_CS_KEY 0x42000070
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#define INTEL_SIP_SMC_FCS_EXPORT_CS_KEY 0xC2000071
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#define INTEL_SIP_SMC_FCS_REMOVE_CS_KEY 0xC2000072
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#define INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO 0xC2000073
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#define INTEL_SIP_SMC_FCS_AES_CRYPT_INIT 0xC2000074
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#define INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE 0x42000075
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#define INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE 0x42000076
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#define INTEL_SIP_SMC_FCS_GET_DIGEST_INIT 0xC2000077
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#define INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE 0xC2000078
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#define INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE 0xC2000079
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#define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE 0x42000091
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#define INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE 0x42000092
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#define INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT 0xC200007A
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#define INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE 0xC200007B
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#define INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE 0xC200007C
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#define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE 0x42000093
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#define INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE 0x42000094
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#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT 0xC200007D
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#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE 0xC200007F
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT 0xC2000080
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE 0xC2000081
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE 0xC2000082
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE 0x42000095
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE 0x42000096
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#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT 0xC2000083
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#define INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE 0xC2000085
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT 0xC2000086
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE 0xC2000087
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE 0xC2000088
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE 0x42000097
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#define INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE 0x42000098
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#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT 0xC2000089
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#define INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE 0xC200008B
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#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
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#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
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#define INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG 0xC2000201
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/* SEU ERR */
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#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
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#define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR 0xC200009A
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/* ATF build version */
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#define INTEL_SIP_SMC_ATF_BUILD_VER 0xC200009B
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#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
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#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
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#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
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#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK 0xF
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/* ECC DBE */
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#define WARM_RESET_WFI_FLAG BIT(31)
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#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
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SYSMGR_ECC_DDR0_MASK |\
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SYSMGR_ECC_DDR1_MASK)
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/* Non-mailbox SMC Call */
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#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
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/**
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* SMC SiP service function identifier for version 2
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* Command code from 0x400 ~ 0x4FF
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*/
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/* V2: Non-mailbox function identifier */
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#define INTEL_SIP_SMC_V2_GET_SVC_VERSION 0xC2000400
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#define INTEL_SIP_SMC_V2_REG_READ 0xC2000401
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#define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402
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#define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403
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#define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404
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#define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR 0xC2000405
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/* V2: Mailbox function identifier */
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#define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420
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#define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE 0xC2000421
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/* SMC function IDs for SiP Service queries */
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_VERSION 0x8200ff03
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/* SiP Service Calls version numbers */
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/*
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* Increase if there is any backward compatibility impact
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*/
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#define SIP_SVC_VERSION_MAJOR 2
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/*
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* Increase if there is new SMC function ID being added
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*/
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#define SIP_SVC_VERSION_MINOR 2
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/* Structure Definitions */
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struct fpga_config_info {
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uint32_t addr;
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int size;
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int size_written;
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uint32_t write_requested;
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int subblocks_sent;
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int block_number;
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};
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typedef enum {
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NO_REQUEST = 0,
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RECONFIGURATION,
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BITSTREAM_AUTH
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} config_type;
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/* Function Definitions */
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bool is_size_4_bytes_aligned(uint32_t size);
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bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
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/* ECC DBE */
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bool cold_reset_for_ecc_dbe(void);
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uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
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/* Secure register access */
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uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval);
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uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
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uint32_t *retval);
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uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
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uint32_t val, uint32_t *retval);
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/* Set RSU update address*/
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uint32_t intel_rsu_update(uint64_t update_address);
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/* Miscellaneous HPS services */
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uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask);
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/* SiP Service handler for version 2 */
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uintptr_t sip_smc_handler_v2(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags);
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#endif /* SOCFPGA_SIP_SVC_H */
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