Jit Loon Lim 646a9a1615 fix(intel): update warm reset routine and bootscratch register usage ... Agilex5 platform: Boot scratch COLD6 register is meant for Customer use only. So, use Intel specific COLD3 register with [5:2]bits to determine the warm reset and SMP boot requests. Also handle the unaligned DEVICE/IO memory store and load in the assembly entrypoint startup code. Agilex, Stratix10, N5X platforms: Use only the LSB 4bits [3:0] of the boot scratch COLD6 register to detect the warm reset request. Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>		2025-01-13 16:31:42 +08:00
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agilex_clock_manager.h	fix(intel): fix hardcoded mpu frequency ticks	2023-12-18 10:12:29 +08:00
agilex_memory_controller.h	fix(intel): update outdated code for Linux direct boot	2024-10-16 23:36:49 +02:00
agilex_mmc.h	plat: intel: set DRVSEL and SMPLSEL for DWMMC	2020-06-08 22:03:34 +00:00
agilex_pinmux.h	feat(intel): setup FPGA interface for Agilex	2022-11-22 23:35:36 +08:00
agilex_system_manager.h	fix(intel): correct macro naming	2024-10-24 19:43:11 +08:00
socfpga_plat_def.h	fix(intel): update warm reset routine and bootscratch register usage	2025-01-13 16:31:42 +08:00