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The patch provide solutions for: 1. Enable BL31 console logs during run-time. 2. Update VAB initialization. 3. Update DDR size accordin to Linux DTS configuration. 4. Solve VAB CCERT address issue. Change-Id: I41eb0fab747de5010d369e845c33a45decb41e21 Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
215 lines
5.3 KiB
C
215 lines
5.3 KiB
C
/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/synopsys/dw_mmc.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "agilex_mmc.h"
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#include "agilex_clock_manager.h"
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#include "agilex_memory_controller.h"
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#include "agilex_pinmux.h"
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#include "ccu/ncore_ccu.h"
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#include "qspi/cadence_qspi.h"
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#include "socfpga_emac.h"
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#include "socfpga_f2sdram_manager.h"
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#include "socfpga_handoff.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_ros.h"
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#include "socfpga_system_manager.h"
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#include "socfpga_vab.h"
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#include "wdt/watchdog.h"
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static struct mmc_device_info mmc_info;
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const mmap_region_t agilex_plat_mmap[] = {
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MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
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MT_MEMORY | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
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MT_DEVICE | MT_RW | MT_NS),
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{0},
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};
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boot_source_type boot_source = BOOT_SOURCE;
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void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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u_register_t x2, u_register_t x4)
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{
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static console_t console;
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handoff reverse_handoff_ptr;
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generic_delay_timer_init();
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if (socfpga_get_handoff(&reverse_handoff_ptr))
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return;
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config_pinmux(&reverse_handoff_ptr);
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config_clkmgr_handoff(&reverse_handoff_ptr);
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enable_nonsecure_access();
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deassert_peripheral_reset();
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config_hps_hs_before_warm_reset();
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watchdog_init(get_wdt_clk());
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console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(),
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PLAT_BAUDRATE, &console);
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socfpga_delay_timer_init();
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init_ncore_ccu();
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socfpga_emac_init();
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init_hard_memory_controller();
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mailbox_init();
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agx_mmc_init();
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if (!intel_mailbox_is_fpga_not_ready()) {
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socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
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FPGA2SOC_MASK);
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}
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}
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void bl2_el3_plat_arch_setup(void)
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{
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unsigned long offset = 0;
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const mmap_region_t bl_regions[] = {
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MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE),
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MAP_REGION_FLAT(BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE),
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#if USE_COHERENT_MEM_BAR
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MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE),
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#endif
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{0},
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};
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setup_page_tables(bl_regions, agilex_plat_mmap);
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/*
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* TODO: mmu enable in latest phase
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*/
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// enable_mmu_el3(0);
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dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
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mmc_info.mmc_dev_type = MMC_IS_SD;
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mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
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/* Request ownership and direct access to QSPI */
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mailbox_hps_qspi_enable();
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switch (boot_source) {
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case BOOT_SOURCE_SDMMC:
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NOTICE("SDMMC boot\n");
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dw_mmc_init(¶ms, &mmc_info);
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socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
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break;
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case BOOT_SOURCE_QSPI:
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NOTICE("QSPI boot\n");
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cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
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QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
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QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
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if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) {
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offset = PLAT_QSPI_DATA_BASE;
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}
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socfpga_io_setup(boot_source, offset);
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break;
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default:
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ERROR("Unsupported boot source\n");
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panic();
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break;
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}
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}
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uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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assert(bl_mem_params);
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#if SOCFPGA_SECURE_VAB_AUTH
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/*
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* VAB Authentication start here.
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* If failed to authenticate, shall not proceed to process BL31 and hang.
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*/
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int ret = 0;
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ret = socfpga_vab_init(image_id);
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if (ret < 0) {
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ERROR("SOCFPGA VAB Authentication failed\n");
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while (1)
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wfi();
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}
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#endif
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switch (image_id) {
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case BL33_IMAGE_ID:
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
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break;
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default:
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break;
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}
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return 0;
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}
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/*******************************************************************************
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* Perform any BL3-1 platform setup code
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******************************************************************************/
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void bl2_platform_setup(void)
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{
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}
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