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https://github.com/ARM-software/arm-trusted-firmware.git
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85229098ab
Fix some clocks and reset binding values. Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
225 lines
5.1 KiB
C
225 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/*
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* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
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*/
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#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
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#define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
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#define CMD_DIV 0
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#define CMD_MUX 1
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#define CMD_CLK 2
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#define CMD_FLEXGEN 3
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#define CMD_ADDR_BIT 0x80000000
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#define CMD_SHIFT 26
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#define CMD_MASK 0xFC000000
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#define CMD_DATA_MASK 0x03FFFFFF
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#define DIV_ID_SHIFT 8
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#define DIV_ID_MASK 0x0000FF00
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#define DIV_DIVN_SHIFT 0
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#define DIV_DIVN_MASK 0x000000FF
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#define MUX_ID_SHIFT 4
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#define MUX_ID_MASK 0x00000FF0
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#define MUX_SEL_SHIFT 0
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#define MUX_SEL_MASK 0x0000000F
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/* CLK define */
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#define CLK_ON_MASK BIT(21)
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#define CLK_ON_SHIFT 21
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#define CLK_ID_MASK GENMASK_32(20, 12)
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#define CLK_ID_SHIFT 12
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#define CLK_NO_DIV_MASK 0x0000080
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#define CLK_DIV_MASK GENMASK_32(10, 5)
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#define CLK_DIV_SHIFT 5
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#define CLK_NO_SEL_MASK 0x00000010
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#define CLK_SEL_MASK GENMASK_32(3, 0)
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#define CLK_SEL_SHIFT 0
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#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\
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((state) << CLK_ON_SHIFT) |\
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((clk_id) << CLK_ID_SHIFT) |\
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((div) << CLK_DIV_SHIFT) |\
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((sel) << CLK_SEL_SHIFT))
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#define CLK_OFF 0
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#define CLK_ON 1
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#define CLK_NODIV 0x00000040
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#define CLK_NOMUX 0x00000010
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/* Flexgen define */
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#define FLEX_ID_SHIFT 13
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#define FLEX_SEL_SHIFT 9
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#define FLEX_PDIV_SHIFT 6
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#define FLEX_FDIV_SHIFT 0
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#define FLEX_ID_MASK GENMASK_32(18, 13)
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#define FLEX_SEL_MASK GENMASK_32(12, 9)
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#define FLEX_PDIV_MASK GENMASK_32(8, 6)
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#define FLEX_FDIV_MASK GENMASK_32(5, 0)
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#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
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((div_id) << DIV_ID_SHIFT |\
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(div)))
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#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
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((mux_id) << MUX_ID_SHIFT |\
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(sel)))
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#define CLK_ADDR_SHIFT 16
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#define CLK_ADDR_MASK 0x7FFF0000
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#define CLK_ADDR_VAL_MASK 0xFFFF
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#define DIV_LSMCU 0
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#define DIV_APB1 1
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#define DIV_APB2 2
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#define DIV_APB3 3
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#define DIV_APB4 4
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#define DIV_APBDBG 5
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#define DIV_RTC 6
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#define DIV_NB 7
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#define MUX_MUXSEL0 0
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#define MUX_MUXSEL1 1
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#define MUX_MUXSEL2 2
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#define MUX_MUXSEL3 3
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#define MUX_MUXSEL4 4
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#define MUX_MUXSEL5 5
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#define MUX_MUXSEL6 6
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#define MUX_MUXSEL7 7
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#define MUX_XBARSEL 8
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#define MUX_RTC 9
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#define MUX_MCO1 10
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#define MUX_MCO2 11
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#define MUX_ADC12 12
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#define MUX_ADC3 13
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#define MUX_USB2PHY1 14
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#define MUX_USB2PHY2 15
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#define MUX_USB3PCIEPHY 16
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#define MUX_DSIBLANE 17
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#define MUX_DSIPHY 18
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#define MUX_LVDSPHY 19
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#define MUX_DTS 20
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#define MUX_D3PER 21
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#define MUX_NB 22
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#define MUXSEL_HSI 0
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#define MUXSEL_HSE 1
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#define MUXSEL_MSI 2
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/* KERNEL source clocks */
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#define MUX_RTC_DISABLED 0x0
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#define MUX_RTC_LSE 0x1
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#define MUX_RTC_LSI 0x2
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#define MUX_RTC_HSE 0x3
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#define MUX_MCO1_FLEX61 0x0
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#define MUX_MCO1_OBSER0 0x1
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#define MUX_MCO2_FLEX62 0x0
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#define MUX_MCO2_OBSER1 0x1
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#define MUX_ADC12_FLEX46 0x0
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#define MUX_ADC12_LSMCU 0x1
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#define MUX_ADC3_FLEX47 0x0
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#define MUX_ADC3_LSMCU 0x1
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#define MUX_ADC3_FLEX46 0x2
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#define MUX_USB2PHY1_FLEX57 0x0
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#define MUX_USB2PHY1_HSE 0x1
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#define MUX_USB2PHY2_FLEX58 0x0
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#define MUX_USB2PHY2_HSE 0x1
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#define MUX_USB3PCIEPHY_FLEX34 0x0
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#define MUX_USB3PCIEPHY_HSE 0x1
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#define MUX_DSIBLANE_DSIPHY 0x0
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#define MUX_DSIBLANE_FLEX27 0x1
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#define MUX_DSIPHY_FLEX28 0x0
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#define MUX_DSIPHY_HSE 0x1
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#define MUX_LVDSPHY_FLEX32 0x0
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#define MUX_LVDSPHY_HSE 0x1
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#define MUX_DTS_HSI 0x0
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#define MUX_DTS_HSE 0x1
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#define MUX_DTS_MSI 0x2
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#define MUX_D3PER_MSI 0x0
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#define MUX_D3PER_LSI 0x1
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#define MUX_D3PER_LSE 0x2
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/* PLLs source clocks */
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#define PLL_SRC_HSI 0x0
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#define PLL_SRC_HSE 0x1
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#define PLL_SRC_MSI 0x2
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#define PLL_SRC_DISABLED 0x3
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/* XBAR source clocks */
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#define XBAR_SRC_PLL4 0x0
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#define XBAR_SRC_PLL5 0x1
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#define XBAR_SRC_PLL6 0x2
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#define XBAR_SRC_PLL7 0x3
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#define XBAR_SRC_PLL8 0x4
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#define XBAR_SRC_HSI 0x5
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#define XBAR_SRC_HSE 0x6
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#define XBAR_SRC_MSI 0x7
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#define XBAR_SRC_HSI_KER 0x8
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#define XBAR_SRC_HSE_KER 0x9
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#define XBAR_SRC_MSI_KER 0xA
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#define XBAR_SRC_SPDIF_SYMB 0xB
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#define XBAR_SRC_I2S 0xC
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#define XBAR_SRC_LSI 0xD
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#define XBAR_SRC_LSE 0xE
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/*
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* Configure a XBAR channel with its clock source
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* channel_nb: XBAR channel number from 0 to 63
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* channel_src: one of the 15 previous XBAR source clocks defines
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* channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
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* can be either 1, 2, 4 or 1024
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* channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
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* from 1 to 64
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*/
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#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\
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((ch) << FLEX_ID_SHIFT) |\
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((sel) << FLEX_SEL_SHIFT) |\
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((pdiv) << FLEX_PDIV_SHIFT) |\
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((fdiv) << FLEX_FDIV_SHIFT))
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/* Register addresses of MCO1 & MCO2 */
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#define MCO1 0x494
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#define MCO2 0x498
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#define MCO_OFF 0
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#define MCO_ON 1
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#define MCO_STATUS_SHIFT 8
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#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\
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((addr) << CLK_ADDR_SHIFT) |\
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((status) << MCO_STATUS_SHIFT) |\
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(sel))
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/* define for st,pll /csg */
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#define SSCG_MODE_CENTER_SPREAD 0
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#define SSCG_MODE_DOWN_SPREAD 1
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/* define for st,drive */
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#define LSEDRV_LOWEST 0
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#define LSEDRV_MEDIUM_LOW 2
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#define LSEDRV_MEDIUM_HIGH 1
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#define LSEDRV_HIGHEST 3
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#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */
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