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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
199 lines
5.8 KiB
C
199 lines
5.8 KiB
C
/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_UART_REGS_H
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#define STM32_UART_REGS_H
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#include <lib/utils_def.h>
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#define USART_CR1 U(0x00)
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#define USART_CR2 U(0x04)
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#define USART_CR3 U(0x08)
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#define USART_BRR U(0x0C)
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#define USART_GTPR U(0x10)
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#define USART_RTOR U(0x14)
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#define USART_RQR U(0x18)
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#define USART_ISR U(0x1C)
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#define USART_ICR U(0x20)
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#define USART_RDR U(0x24)
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#define USART_TDR U(0x28)
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#define USART_PRESC U(0x2C)
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/* USART_CR1 register fields */
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#define USART_CR1_UE BIT(0)
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#define USART_CR1_UESM BIT(1)
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#define USART_CR1_RE BIT(2)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_IDLEIE BIT(4)
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#define USART_CR1_RXNEIE BIT(5)
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#define USART_CR1_TCIE BIT(6)
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#define USART_CR1_TXEIE BIT(7)
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#define USART_CR1_PEIE BIT(8)
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#define USART_CR1_PS BIT(9)
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#define USART_CR1_PCE BIT(10)
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#define USART_CR1_WAKE BIT(11)
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#define USART_CR1_M (BIT(28) | BIT(12))
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#define USART_CR1_M0 BIT(12)
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#define USART_CR1_MME BIT(13)
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#define USART_CR1_CMIE BIT(14)
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_DEDT GENMASK(20, 16)
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#define USART_CR1_DEDT_0 BIT(16)
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#define USART_CR1_DEDT_1 BIT(17)
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#define USART_CR1_DEDT_2 BIT(18)
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#define USART_CR1_DEDT_3 BIT(19)
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#define USART_CR1_DEDT_4 BIT(20)
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#define USART_CR1_DEAT GENMASK(25, 21)
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#define USART_CR1_DEAT_0 BIT(21)
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#define USART_CR1_DEAT_1 BIT(22)
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#define USART_CR1_DEAT_2 BIT(23)
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#define USART_CR1_DEAT_3 BIT(24)
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#define USART_CR1_DEAT_4 BIT(25)
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#define USART_CR1_RTOIE BIT(26)
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#define USART_CR1_EOBIE BIT(27)
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#define USART_CR1_M1 BIT(28)
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#define USART_CR1_FIFOEN BIT(29)
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#define USART_CR1_TXFEIE BIT(30)
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#define USART_CR1_RXFFIE BIT(31)
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/* USART_CR2 register fields */
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#define USART_CR2_SLVEN BIT(0)
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#define USART_CR2_DIS_NSS BIT(3)
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#define USART_CR2_ADDM7 BIT(4)
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#define USART_CR2_LBDL BIT(5)
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#define USART_CR2_LBDIE BIT(6)
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#define USART_CR2_LBCL BIT(8)
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#define USART_CR2_CPHA BIT(9)
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#define USART_CR2_CPOL BIT(10)
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#define USART_CR2_CLKEN BIT(11)
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#define USART_CR2_STOP GENMASK(13, 12)
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#define USART_CR2_STOP_0 BIT(12)
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#define USART_CR2_STOP_1 BIT(13)
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#define USART_CR2_LINEN BIT(14)
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#define USART_CR2_SWAP BIT(15)
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#define USART_CR2_RXINV BIT(16)
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#define USART_CR2_TXINV BIT(17)
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#define USART_CR2_DATAINV BIT(18)
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#define USART_CR2_MSBFIRST BIT(19)
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#define USART_CR2_ABREN BIT(20)
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#define USART_CR2_ABRMODE GENMASK(22, 21)
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#define USART_CR2_ABRMODE_0 BIT(21)
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#define USART_CR2_ABRMODE_1 BIT(22)
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#define USART_CR2_RTOEN BIT(23)
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#define USART_CR2_ADD GENMASK(31, 24)
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/* USART_CR3 register fields */
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#define USART_CR3_EIE BIT(0)
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#define USART_CR3_IREN BIT(1)
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#define USART_CR3_IRLP BIT(2)
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#define USART_CR3_HDSEL BIT(3)
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#define USART_CR3_NACK BIT(4)
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#define USART_CR3_SCEN BIT(5)
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#define USART_CR3_DMAR BIT(6)
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#define USART_CR3_DMAT BIT(7)
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#define USART_CR3_RTSE BIT(8)
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#define USART_CR3_CTSE BIT(9)
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#define USART_CR3_CTSIE BIT(10)
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#define USART_CR3_ONEBIT BIT(11)
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#define USART_CR3_OVRDIS BIT(12)
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#define USART_CR3_DDRE BIT(13)
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#define USART_CR3_DEM BIT(14)
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#define USART_CR3_DEP BIT(15)
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#define USART_CR3_SCARCNT GENMASK(19, 17)
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#define USART_CR3_SCARCNT_0 BIT(17)
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#define USART_CR3_SCARCNT_1 BIT(18)
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#define USART_CR3_SCARCNT_2 BIT(19)
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#define USART_CR3_WUS GENMASK(21, 20)
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#define USART_CR3_WUS_0 BIT(20)
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#define USART_CR3_WUS_1 BIT(21)
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#define USART_CR3_WUFIE BIT(22)
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#define USART_CR3_TXFTIE BIT(23)
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#define USART_CR3_TCBGTIE BIT(24)
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#define USART_CR3_RXFTCFG GENMASK(27, 25)
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#define USART_CR3_RXFTCFG_0 BIT(25)
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#define USART_CR3_RXFTCFG_1 BIT(26)
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#define USART_CR3_RXFTCFG_2 BIT(27)
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#define USART_CR3_RXFTIE BIT(28)
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#define USART_CR3_TXFTCFG GENMASK(31, 29)
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#define USART_CR3_TXFTCFG_0 BIT(29)
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#define USART_CR3_TXFTCFG_1 BIT(30)
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#define USART_CR3_TXFTCFG_2 BIT(31)
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/* USART_BRR register fields */
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#define USART_BRR_DIV_FRACTION GENMASK(3, 0)
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#define USART_BRR_DIV_MANTISSA GENMASK(15, 4)
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/* USART_GTPR register fields */
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#define USART_GTPR_PSC GENMASK(7, 0)
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#define USART_GTPR_GT GENMASK(15, 8)
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/* USART_RTOR register fields */
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#define USART_RTOR_RTO GENMASK(23, 0)
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#define USART_RTOR_BLEN GENMASK(31, 24)
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/* USART_RQR register fields */
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#define USART_RQR_ABRRQ BIT(0)
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#define USART_RQR_SBKRQ BIT(1)
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#define USART_RQR_MMRQ BIT(2)
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#define USART_RQR_RXFRQ BIT(3)
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#define USART_RQR_TXFRQ BIT(4)
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/* USART_ISR register fields */
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#define USART_ISR_PE BIT(0)
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#define USART_ISR_FE BIT(1)
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#define USART_ISR_NE BIT(2)
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#define USART_ISR_ORE BIT(3)
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#define USART_ISR_IDLE BIT(4)
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#define USART_ISR_RXNE BIT(5)
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#define USART_ISR_TC BIT(6)
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#define USART_ISR_TXE BIT(7)
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#define USART_ISR_LBDF BIT(8)
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#define USART_ISR_CTSIF BIT(9)
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#define USART_ISR_CTS BIT(10)
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#define USART_ISR_RTOF BIT(11)
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#define USART_ISR_EOBF BIT(12)
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#define USART_ISR_UDR BIT(13)
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#define USART_ISR_ABRE BIT(14)
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#define USART_ISR_ABRF BIT(15)
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#define USART_ISR_BUSY BIT(16)
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#define USART_ISR_CMF BIT(17)
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#define USART_ISR_SBKF BIT(18)
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#define USART_ISR_RWU BIT(19)
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#define USART_ISR_WUF BIT(20)
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#define USART_ISR_TEACK BIT(21)
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#define USART_ISR_REACK BIT(22)
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#define USART_ISR_TXFE BIT(23)
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#define USART_ISR_RXFF BIT(24)
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#define USART_ISR_TCBGT BIT(25)
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#define USART_ISR_RXFT BIT(26)
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#define USART_ISR_TXFT BIT(27)
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/* USART_ICR register fields */
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#define USART_ICR_PECF BIT(0)
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#define USART_ICR_FECF BIT(1)
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#define USART_ICR_NCF BIT(2)
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#define USART_ICR_ORECF BIT(3)
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#define USART_ICR_IDLECF BIT(4)
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#define USART_ICR_TCCF BIT(6)
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#define USART_ICR_TCBGT BIT(7)
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#define USART_ICR_LBDCF BIT(8)
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#define USART_ICR_CTSCF BIT(9)
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#define USART_ICR_RTOCF BIT(11)
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#define USART_ICR_EOBCF BIT(12)
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#define USART_ICR_UDRCF BIT(13)
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#define USART_ICR_CMCF BIT(17)
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#define USART_ICR_WUCF BIT(20)
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/* USART_RDR register fields */
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#define USART_RDR_RDR GENMASK(8, 0)
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/* USART_TDR register fields */
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#define USART_TDR_TDR GENMASK(8, 0)
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/* USART_PRESC register fields */
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#define USART_PRESC_PRESCALER GENMASK(3, 0)
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#endif /* STM32_UART_REGS_H */
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