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https://github.com/ARM-software/arm-trusted-firmware.git
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d30312a2dc
These registers are 32-bit registers. When accessing them using pointers, when should explicitely divide the fixed offsets GPDIR_REG_OFFSET and GPDAT_REG_OFFSET by 4 to land on the correct address. While set_gpio_bit() did this correctly, clr_gpio_bit() did not. Even though GPDIR_REG_OFFSET = 0x0, shift it as well for consistency with GPDAT_REG_OFFSET. Change-Id: I5b8787d8424f83462ad4bb0f2141370ca28eaf34 Signed-off-by: Antonin Godard <antoningodard@pm.me>
145 lines
3.2 KiB
C
145 lines
3.2 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <nxp_gpio.h>
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static gpio_init_info_t *gpio_init_info;
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void gpio_init(gpio_init_info_t *gpio_init_data)
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{
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gpio_init_info = gpio_init_data;
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}
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/* This function set GPIO pin for raising POVDD. */
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int set_gpio_bit(uint32_t *gpio_base_addr,
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uint32_t bit_num)
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{
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uint32_t val = 0U;
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uint32_t *gpdir = NULL;
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uint32_t *gpdat = NULL;
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if (gpio_init_info == NULL) {
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ERROR("GPIO is not initialized.\n");
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return GPIO_FAILURE;
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}
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/* Divide by 4 since we're operating on 32-bit pointer addresses. */
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gpdir = gpio_base_addr + (GPDIR_REG_OFFSET >> 2);
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gpdat = gpio_base_addr + (GPDAT_REG_OFFSET >> 2);
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/*
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* Set the corresponding bit in direction register
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* to configure the GPIO as output.
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*/
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val = gpio_read32(gpdir);
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val = val | bit_num;
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gpio_write32(gpdir, val);
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/* Set the corresponding bit in GPIO data register */
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val = gpio_read32(gpdat);
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val = val | bit_num;
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gpio_write32(gpdat, val);
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val = gpio_read32(gpdat);
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if ((val & bit_num) == 0U) {
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return GPIO_FAILURE;
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}
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return GPIO_SUCCESS;
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}
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/* This function reset GPIO pin set for raising POVDD. */
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int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num)
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{
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uint32_t val = 0U;
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uint32_t *gpdir = NULL;
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uint32_t *gpdat = NULL;
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if (gpio_init_info == NULL) {
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ERROR("GPIO is not initialized.\n");
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return GPIO_FAILURE;
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}
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/* Divide by 4 since we're operating on 32-bit pointer addresses. */
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gpdir = gpio_base_addr + (GPDIR_REG_OFFSET >> 2);
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gpdat = gpio_base_addr + (GPDAT_REG_OFFSET >> 2);
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/*
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* Reset the corresponding bit in direction and data register
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* to configure the GPIO as input.
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*/
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val = gpio_read32(gpdat);
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val = val & ~(bit_num);
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gpio_write32(gpdat, val);
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val = gpio_read32(gpdat);
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val = gpio_read32(gpdir);
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val = val & ~(bit_num);
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gpio_write32(gpdir, val);
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val = gpio_read32(gpdat);
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if ((val & bit_num) != 0U) {
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return GPIO_FAILURE;
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}
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return GPIO_SUCCESS;
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}
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uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num)
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{
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uint32_t *ret_gpio;
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uint32_t povdd_gpio_val = 0U;
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uint32_t gpio_num = 0U;
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if (gpio_init_info == NULL) {
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ERROR("GPIO is not initialized.\n");
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}
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/*
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* Subtract 1 from fuse_hdr povdd_gpio value as
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* for 0x1 value, bit 0 is to be set
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* for 0x20 value i.e 32, bit 31 i.e. 0x1f is to be set.
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* 0x1f - 0x00 : GPIO_1
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* 0x3f - 0x20 : GPIO_2
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* 0x5f - 0x40 : GPIO_3
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* 0x7f - 0x60 : GPIO_4
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*/
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povdd_gpio_val = (povdd_gpio - 1U) & GPIO_SEL_MASK;
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/* Right shift by 5 to divide by 32 */
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gpio_num = povdd_gpio_val >> GPIO_ID_BASE_ADDR_SHIFT;
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*bit_num = 1U << (GPIO_BITS_PER_BASE_REG
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- (povdd_gpio_val & GPIO_BIT_MASK)
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- 1U);
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switch (gpio_num) {
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case GPIO_0:
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ret_gpio = (uint32_t *) gpio_init_info->gpio1_base_addr;
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break;
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case GPIO_1:
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ret_gpio = (uint32_t *) gpio_init_info->gpio2_base_addr;
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break;
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case GPIO_2:
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ret_gpio = (uint32_t *) gpio_init_info->gpio3_base_addr;
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break;
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case GPIO_3:
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ret_gpio = (uint32_t *) gpio_init_info->gpio4_base_addr;
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break;
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default:
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ret_gpio = NULL;
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}
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if (ret_gpio == NULL) {
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INFO("GPIO_NUM = %d doesn't exist.\n", gpio_num);
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}
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return ret_gpio;
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}
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