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https://github.com/ARM-software/arm-trusted-firmware.git
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550a06dfd1
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by: Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* Those are parameters for xfi mode, which need to be tune for each board type.
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* For known DB boards the parameters was already calibrated and placed under
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* the plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h
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*/
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struct xfi_params {
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uint8_t g1_ffe_res_sel;
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uint8_t g1_ffe_cap_sel;
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uint8_t align90;
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uint8_t g1_dfe_res;
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uint8_t g1_amp;
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uint8_t g1_emph;
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uint8_t g1_emph_en;
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uint8_t g1_tx_amp_adj;
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uint8_t g1_tx_emph_en;
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uint8_t g1_tx_emph;
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uint8_t g1_rx_selmuff;
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uint8_t g1_rx_selmufi;
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uint8_t g1_rx_selmupf;
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uint8_t g1_rx_selmupi;
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_Bool valid;
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};
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struct sata_params {
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uint8_t g1_amp;
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uint8_t g2_amp;
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uint8_t g3_amp;
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uint8_t g1_emph;
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uint8_t g2_emph;
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uint8_t g3_emph;
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uint8_t g1_emph_en;
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uint8_t g2_emph_en;
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uint8_t g3_emph_en;
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uint8_t g1_tx_amp_adj;
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uint8_t g2_tx_amp_adj;
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uint8_t g3_tx_amp_adj;
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uint8_t g1_tx_emph_en;
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uint8_t g2_tx_emph_en;
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uint8_t g3_tx_emph_en;
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uint8_t g1_tx_emph;
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uint8_t g2_tx_emph;
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uint8_t g3_tx_emph;
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uint8_t g3_dfe_res;
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uint8_t g3_ffe_res_sel;
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uint8_t g3_ffe_cap_sel;
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uint8_t align90;
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uint8_t g1_rx_selmuff;
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uint8_t g2_rx_selmuff;
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uint8_t g3_rx_selmuff;
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uint8_t g1_rx_selmufi;
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uint8_t g2_rx_selmufi;
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uint8_t g3_rx_selmufi;
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uint8_t g1_rx_selmupf;
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uint8_t g2_rx_selmupf;
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uint8_t g3_rx_selmupf;
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uint8_t g1_rx_selmupi;
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uint8_t g2_rx_selmupi;
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uint8_t g3_rx_selmupi;
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uint8_t polarity_invert;
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_Bool valid;
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};
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struct usb_params {
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uint8_t polarity_invert;
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};
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int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
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uint8_t comphy_index);
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int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
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uint8_t comphy_index, uint64_t comphy_mode);
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int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
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uint64_t comphy_mode,
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uint64_t comphy_train_base);
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int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
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uint8_t comphy_index);
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int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
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uint32_t comphy_mode, uint32_t command);
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#define COMPHY_POLARITY_NO_INVERT 0
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#define COMPHY_POLARITY_TXD_INVERT 1
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#define COMPHY_POLARITY_RXD_INVERT 2
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