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drivers: marvell: comphy: add rx training on 10G port

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This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
This commit is contained in:
Alex Evraev 2020-06-24 22:24:56 +03:00 • committed by Manish Pandey
parent b5a0663771
commit 550a06dfd1
3 changed files with 30 additions and 9 deletions
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26
drivers/marvell/comphy/phy-comphy-cp110.c
View file

@ -61,6 +61,11 @@
SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET)
#define SAR_STATUS_0_REG 200
#define DFX_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + DFX_BASE)
/* Common Phy training */
#define COMPHY_TRX_TRAIN_COMPHY_OFFS 0x1000
#define COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE 0x1
#define COMPHY_TRX_RELATIVE_ADDR(comphy_index) (comphy_train_base + \
(comphy_index) * COMPHY_TRX_TRAIN_COMPHY_OFFS)
/* The same Units Soft Reset Config register are accessed in all PCIe ports
* initialization, so a spin lock is defined in case when more than 1 CPUs
@ -829,7 +834,8 @@ static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base,
static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
uint8_t comphy_index,
uint32_t comphy_mode)
uint32_t comphy_mode,
uint64_t comphy_train_base)
{
uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
@ -837,7 +843,6 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
uint8_t ap_nr, cp_nr;
debug_enter();
mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
if (rx_trainng_done[ap_nr][cp_nr][comphy_index]) {
@ -1234,6 +1239,14 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
/* Force rx training on 10G port */
data = mmio_read_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index));
data |= COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
mdelay(200);
data &= ~COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
debug_exit();
return ret;
@ -2348,8 +2361,10 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base,
return 0;
}
int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
uint64_t comphy_mode)
int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
uint8_t comphy_index,
uint64_t comphy_mode,
uint64_t comphy_train_base)
{
int mode = COMPHY_GET_MODE(comphy_mode);
int err = 0;
@ -2373,7 +2388,8 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
case (COMPHY_SFI_MODE):
err = mvebu_cp110_comphy_xfi_power_on(comphy_base,
comphy_index,
comphy_mode);
comphy_mode,
comphy_train_base);
break;
case (COMPHY_PCIE_MODE):
err = mvebu_cp110_comphy_pcie_power_on(comphy_base,

5
drivers/marvell/comphy/phy-comphy-cp110.h
View file

@ -89,8 +89,9 @@ int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
uint8_t comphy_index, uint64_t comphy_mode);
int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
uint8_t comphy_index, uint64_t comphy_mode);
int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
uint64_t comphy_mode,
uint64_t comphy_train_base);
int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,

8
plat/marvell/armada/common/mrvl_sip_svc.c
View file

@ -50,6 +50,9 @@
#define MVEBU_COMPHY_OFFSET 0x441000
#define MVEBU_CP_BASE_MASK (~0xffffff)
/* Common PHY register */
#define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS 0x120a2c
/* This macro is used to identify COMPHY related calls from SMC function ID */
#define is_comphy_fid(fid) \
((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
@ -76,7 +79,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
void *handle,
u_register_t flags)
{
u_register_t ret, read;
u_register_t ret, read, x5 = x1;
uint32_t w2[2] = {0, 0};
int i;
@ -91,6 +94,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
SMC_RET1(handle, SMC_UNK);
}
x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS;
x1 += MVEBU_COMPHY_OFFSET;
if (x2 >= MAX_LANE_NR) {
@ -105,7 +109,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
/* Comphy related FID's */
case MV_SIP_COMPHY_POWER_ON:
/* x1: comphy_base, x2: comphy_index, x3: comphy_mode */
ret = mvebu_cp110_comphy_power_on(x1, x2, x3);
ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5);
SMC_RET1(handle, ret);
case MV_SIP_COMPHY_POWER_OFF:
/* x1: comphy_base, x2: comphy_index */