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arm-trusted-firmware/lib/cpus/aarch32
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Heiko Stuebner c6c10b02b8 Fixup register handling in aarch32 reset_handler 
The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.

Adapt to use r8 and adapt the comment about registers allowed
to clober.

I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.

Fixes: a6f340fe58 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-08 15:35:30 +00:00
..
aem_generic.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a5.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a7.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a9.S Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 2018-01-18 10:36:25 +00:00
cortex_a12.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a15.S Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 2018-01-18 10:36:25 +00:00
cortex_a17.S Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 2018-01-18 10:36:25 +00:00
cortex_a32.S Make errata reporting mandatory for CPU files 2018-10-29 09:54:32 +00:00
cortex_a53.S Cortex-A53: Workarounds for 819472, 824069 and 827319 2019-02-28 09:56:58 +00:00
cortex_a57.S Cortex-A57: Implement workaround for erratum 817169 2019-02-28 09:56:58 +00:00
cortex_a72.S Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
cpu_helpers.S Fixup register handling in aarch32 reset_handler 2019-03-08 15:35:30 +00:00