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c69f815b09
Up until now we relied on the GICs used in our FPGA images to be GICv3 compliant, without the "direct virtual injection" feature (aka GICv4) enabled. To support newer images which have GICv4 compliant GICs, enable the newly introduced GICv4 detection code, and use that also when we adjust the redistributor region size in the devicetree. This allows the same BL31 image to be used with GICv3 or GICv4 FPGA images. Change-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
32 lines
726 B
C
32 lines
726 B
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FPGA_PRIVATE_H
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#define FPGA_PRIVATE_H
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#include "../fpga_def.h"
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#include <platform_def.h>
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#define C_RUNTIME_READY_KEY (0xaa55aa55)
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#define VALID_MPID (1U)
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#define FPGA_MAX_DTB_SIZE 0x10000
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#ifndef __ASSEMBLER__
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extern unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT];
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void fpga_console_init(void);
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void plat_fpga_gic_init(void);
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void fpga_pwr_gic_on_finish(void);
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void fpga_pwr_gic_off(void);
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unsigned int plat_fpga_calc_core_pos(uint32_t mpid);
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unsigned int fpga_get_nr_gic_cores(void);
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uintptr_t fpga_get_redist_size(void);
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#endif /* __ASSEMBLER__ */
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#endif /* FPGA_PRIVATE_H */
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