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c060b5337a
Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0 and r2p0 of the Cortex-X2 processor core. Cortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I64bed2fd5b7e12932d6de2ae668786e689885188
288 lines
7.2 KiB
ArmAsm
288 lines
7.2 KiB
ArmAsm
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x2.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex X2 Errata #2002765.
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* This applies to revisions r0p0, r1p0, and r2p0 and
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* is open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_x2_2002765_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2002765
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cbz x0, 1f
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ldr x0, =0x6
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msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
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ldr x0, =0xF3A08002
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msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
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ldr x0, =0xFFF0F7FE
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msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
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ldr x0, =0x40000001003ff
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msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
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isb
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1:
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ret x17
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endfunc errata_cortex_x2_2002765_wa
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func check_errata_2002765
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/* Applies to r0p0 - r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2002765
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/* --------------------------------------------------
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* Errata Workaround for Cortex X2 Errata #2058056.
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* This applies to revisions r0p0, r1p0, and r2p0 and
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* is open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_x2_2058056_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2058056
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cbz x0, 1f
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mrs x1, CORTEX_X2_CPUECTLR2_EL1
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mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
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msr CORTEX_X2_CPUECTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_cortex_x2_2058056_wa
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func check_errata_2058056
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/* Applies to r0p0 - r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2058056
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/* --------------------------------------------------
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* Errata Workaround for Cortex X2 Errata #2083908.
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* This applies to revision r2p0 and is open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x2, x17
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* --------------------------------------------------
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*/
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func errata_cortex_x2_2083908_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2083908
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cbz x0, 1f
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/* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
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mrs x1, CORTEX_X2_CPUACTLR5_EL1
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orr x1, x1, #BIT(13)
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msr CORTEX_X2_CPUACTLR5_EL1, x1
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1:
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ret x17
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endfunc errata_cortex_x2_2083908_wa
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func check_errata_2083908
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/* Applies to r2p0 */
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mov x1, #0x20
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mov x2, #0x20
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b cpu_rev_var_range
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endfunc check_errata_2083908
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/* --------------------------------------------------
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* Errata Workaround for Cortex-X2 Errata 2017096.
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* This applies only to revisions r0p0, r1p0 and r2p0
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* and is fixed in r2p1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_x2_2017096_wa
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/* Compare x0 against revision r0p0 to r2p0 */
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mov x17, x30
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bl check_errata_2017096
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cbz x0, 1f
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mrs x1, CORTEX_X2_CPUECTLR_EL1
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orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
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msr CORTEX_X2_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_x2_2017096_wa
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func check_errata_2017096
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/* Applies to r0p0, r1p0, r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2017096
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/* --------------------------------------------------
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* Errata Workaround for Cortex-X2 Errata 2081180.
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* This applies to revision r0p0, r1p0 and r2p0
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* and is fixed in r2p1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_x2_2081180_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2081180
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x3
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xF3A08002
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFFF0F7FE
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x10002001003FF
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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ldr x0, =0x4
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xBF200000
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFFEF0000
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x10002001003F3
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_x2_2081180_wa
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func check_errata_2081180
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/* Applies to r0p0, r1p0 and r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2081180
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x2_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_X2_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_x2_core_pwr_dwn
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/*
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* Errata printing function for Cortex X2. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_x2_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_X2_2002765, cortex_x2, 2002765
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report_errata ERRATA_X2_2058056, cortex_x2, 2058056
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report_errata ERRATA_X2_2083908, cortex_x2, 2083908
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report_errata ERRATA_X2_2017096, cortex_x2, 2017096
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report_errata ERRATA_X2_2081180, cortex_x2, 2081180
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_x2_errata_report
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#endif
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func cortex_x2_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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isb
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/* Get the CPU revision and stash it in x18. */
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_X2_2002765
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mov x0, x18
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bl errata_cortex_x2_2002765_wa
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#endif
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#if ERRATA_X2_2058056
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mov x0, x18
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bl errata_cortex_x2_2058056_wa
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#endif
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#if ERRATA_X2_2083908
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mov x0, x18
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bl errata_cortex_x2_2083908_wa
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#endif
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#if ERRATA_X2_2017096
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mov x0, x18
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bl errata_x2_2017096_wa
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#endif
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#if ERRATA_X2_2081180
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mov x0, x18
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bl errata_x2_2081180_wa
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#endif
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ret x19
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endfunc cortex_x2_reset_func
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/* ---------------------------------------------
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* This function provides Cortex X2 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x2_regs, "aS"
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cortex_x2_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x2_cpu_reg_dump
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adr x6, cortex_x2_regs
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mrs x8, CORTEX_X2_CPUECTLR_EL1
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ret
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endfunc cortex_x2_cpu_reg_dump
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declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
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cortex_x2_reset_func, \
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cortex_x2_core_pwr_dwn
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