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fix(errata): workaround for Cortex-X2 errata 2081180
Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0 and r2p0 of the Cortex-X2 processor core. Cortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I64bed2fd5b7e12932d6de2ae668786e689885188
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@ -458,6 +458,10 @@ For Cortex-X2, the following errata build flags are defined :
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Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
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r2p0 of the CPU, it is fixed in r2p1.
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- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
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Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
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r2p0 of the CPU, it is fixed in r2p1.
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DSU Errata Workarounds
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----------------------
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@ -35,4 +35,12 @@
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
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/*******************************************************************************
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* CPU Implementation Specific Selected Instruction registers
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******************************************************************************/
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#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* CORTEX_X2_H */
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@ -141,6 +141,49 @@ func check_errata_2017096
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b cpu_rev_var_ls
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endfunc check_errata_2017096
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/* --------------------------------------------------
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* Errata Workaround for Cortex-X2 Errata 2081180.
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* This applies to revision r0p0, r1p0 and r2p0
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* and is fixed in r2p1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_x2_2081180_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2081180
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x3
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xF3A08002
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFFF0F7FE
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x10002001003FF
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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ldr x0, =0x4
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xBF200000
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFFEF0000
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x10002001003F3
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_x2_2081180_wa
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func check_errata_2081180
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/* Applies to r0p0, r1p0 and r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2081180
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -175,6 +218,7 @@ func cortex_x2_errata_report
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report_errata ERRATA_X2_2058056, cortex_x2, 2058056
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report_errata ERRATA_X2_2083908, cortex_x2, 2083908
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report_errata ERRATA_X2_2017096, cortex_x2, 2017096
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report_errata ERRATA_X2_2081180, cortex_x2, 2081180
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ldp x8, x30, [sp], #16
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ret
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@ -212,6 +256,11 @@ func cortex_x2_reset_func
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bl errata_x2_2017096_wa
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#endif
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#if ERRATA_X2_2081180
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mov x0, x18
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bl errata_x2_2081180_wa
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#endif
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ret x19
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endfunc cortex_x2_reset_func
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@ -512,6 +512,11 @@ ERRATA_X2_2083908 ?=0
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# r2p1.
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ERRATA_X2_2017096 ?=0
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# Flag to apply erratum 2081180 workaround during reset. This erratum applies
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# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
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# r2p1.
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ERRATA_X2_2081180 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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ERRATA_DSU_798953 ?=0
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@ -953,6 +958,10 @@ $(eval $(call add_define,ERRATA_X2_2083908))
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$(eval $(call assert_boolean,ERRATA_X2_2017096))
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$(eval $(call add_define,ERRATA_X2_2017096))
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# Process ERRATA_X2_2081180 flag
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$(eval $(call assert_boolean,ERRATA_X2_2081180))
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$(eval $(call add_define,ERRATA_X2_2081180))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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