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af5ae9a73f
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-3090091/latest/ Change-Id: Ib830470747822cac916750c01684a65cb5efc15b Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
71 lines
2.1 KiB
ArmAsm
71 lines
2.1 KiB
ArmAsm
/*
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* Copyright (c) 2024-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a720_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_cortex_a720_ae_3699562
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add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET
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check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0)
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cpu_reset_func_start cortex_a720_ae
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_a720_ae
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a720_ae_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_a720_ae_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-A720AE specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a720_ae_regs, "aS"
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cortex_a720_ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a720_ae_cpu_reg_dump
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adr x6, cortex_a720_ae_regs
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mrs x8, CORTEX_A720_AE_CPUECTLR_EL1
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ret
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endfunc cortex_a720_ae_cpu_reg_dump
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declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \
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cortex_a720_ae_reset_func, \
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cortex_a720_ae_core_pwr_dwn
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