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https://github.com/ARM-software/arm-trusted-firmware.git
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bb801857ea
Introduce a new helper to toggle bits in assembly. This allows us to call the workaround twice, with the first call setting the workaround and second undoing it. This allows the (errata) workaround functions to be used to both apply and undo the mitigation. This is applied to functions where the undo part will be required in follow-up patches. Change-Id: I058bad58f5949b2d5fe058101410e33b6be1b8ba Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
83 lines
2.4 KiB
ArmAsm
83 lines
2.4 KiB
ArmAsm
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_gelas.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Gelas must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_func_start cortex_gelas
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/* ----------------------------------------------------
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* Disable speculative loads
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* ----------------------------------------------------
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*/
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msr SSBS, xzr
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cpu_reset_func_end cortex_gelas
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_gelas_core_pwr_dwn
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#if ENABLE_SME_FOR_NS
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/* ---------------------------------------------------
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* Disable SME if enabled and supported
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* ---------------------------------------------------
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*/
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mrs x0, ID_AA64PFR1_EL1
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ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
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#ID_AA64PFR1_EL1_SME_WIDTH
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cmp x0, #SME_NOT_IMPLEMENTED
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b.eq 1f
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msr CORTEX_GELAS_SVCRSM, xzr
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msr CORTEX_GELAS_SVCRZA, xzr
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1:
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#endif
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/* ---------------------------------------------------
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* Flip CPU power down bit in power control register.
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* It will be set on powerdown and cleared on wakeup
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* ---------------------------------------------------
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*/
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sysreg_bit_toggle CORTEX_GELAS_CPUPWRCTLR_EL1, \
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CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_gelas_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Gelas specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_gelas_regs, "aS"
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cortex_gelas_regs: /* The ASCII list of register names to be reported */
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.asciz "imp_cpuectlr_el1", ""
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func cortex_gelas_cpu_reg_dump
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adr x6, cortex_gelas_regs
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mrs x8, CORTEX_GELAS_IMP_CPUECTLR_EL1
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ret
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endfunc cortex_gelas_cpu_reg_dump
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declare_cpu_ops cortex_gelas, CORTEX_GELAS_MIDR, \
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cortex_gelas_reset_func, \
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cortex_gelas_core_pwr_dwn
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