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11c48370bd
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
63 lines
2.2 KiB
C
63 lines
2.2 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_N1_H
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#define NEOVERSE_N1_H
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#include <lib/utils_def.h>
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/* Neoverse N1 MIDR for revision 0 */
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#define NEOVERSE_N1_MIDR U(0x410fd0c0)
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
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#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
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#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4)
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#define NEOVERSE_N1_AMU_NR_COUNTERS U(5)
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#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
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#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
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#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
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#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
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#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
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#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
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#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
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#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
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#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
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/* Instruction patching registers */
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#define CPUPSELR_EL3 S3_6_C15_C8_0
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#define CPUPCR_EL3 S3_6_C15_C8_1
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#define CPUPOR_EL3 S3_6_C15_C8_2
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#define CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* NEOVERSE_N1_H */
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