mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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b3d2850842
BL2: Update BL2 init flow, Timer base address, avoid cache flush of BL2 image descriptors BL31: Remove re-init of CCU and other misc updates Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
114 lines
3.8 KiB
C
114 lines
3.8 KiB
C
/*
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* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_SOCFPGA_DEF_H
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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#include <lib/utils_def.h>
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#include "s10_system_manager.h"
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define PLAT_PRIMARY_CPU 0
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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#define PLAT_TIMER_BASE_ADDR 0xFFD01000
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000
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/* QSPI Setting */
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#define CAD_QSPIDATA_OFST 0xff900000
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#define CAD_QSPI_OFFSET 0xff8d2000
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/* Register Mapping */
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#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
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#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
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#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
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#define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000
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#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
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#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define DRAM_BASE (0x0)
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#define DRAM_SIZE (0x80000000)
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#define OCRAM_BASE (0xFFE00000)
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#define OCRAM_SIZE (0x00040000)
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#define MEM64_BASE (0x0100000000)
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#define MEM64_SIZE (0x1F00000000)
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#define DEVICE1_BASE (0x80000000)
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#define DEVICE1_SIZE (0x60000000)
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#define DEVICE2_BASE (0xF7000000)
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#define DEVICE2_SIZE (0x08E00000)
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#define DEVICE3_BASE (0xFFFC0000)
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#define DEVICE3_SIZE (0x00008000)
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#define DEVICE4_BASE (0x2000000000)
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#define DEVICE4_SIZE (0x0100000000)
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe2b000)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0xFFC02000)
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#define PLAT_UART1_BASE (0xFFC02100)
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/*******************************************************************************
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* WDT related constants
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******************************************************************************/
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#define WDT_BASE (0xFFD00200)
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0xFFFC0000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
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#define PLAT_GICR_BASE 0
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
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#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS mmc_read_blocks
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#define SDMMC_WRITE_BLOCKS mmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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* is done and HPS should trigger warm reset via RMR_EL3.
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******************************************************************************/
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#define L2_RESET_DONE_REG 0xFFD12218
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/* Platform specific system counter */
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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#endif /* PLATSOCFPGA_DEF_H */
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