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811af8b768
There are additional instruction needed to enable the global timer. This fixes the global timer initialization Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#define SOCFPGA_GLOBAL_TIMER 0xffd01000
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#define SOCFPGA_GLOBAL_TIMER_EN 0x3
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/********************************************************************
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* The timer delay function
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********************************************************************/
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static uint32_t socfpga_get_timer_value(void)
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{
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/*
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* Generic delay timer implementation expects the timer to be a down
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* counter. We apply bitwise NOT operator to the tick values returned
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* by read_cntpct_el0() to simulate the down counter. The value is
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* clipped from 64 to 32 bits.
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*/
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return (uint32_t)(~read_cntpct_el0());
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}
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static const timer_ops_t plat_timer_ops = {
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.get_timer_value = socfpga_get_timer_value,
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.clk_mult = 1,
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.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
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};
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void socfpga_delay_timer_init(void)
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{
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timer_init(&plat_timer_ops);
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mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
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asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN));
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asm volatile("msr cntp_tval_el0, %0" : : "r" (~0));
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}
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