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arm-trusted-firmware/plat/intel/soc/common
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Abdul Halim, Muhammad Hadi Asyrafi d57318b7c9 intel: common: Fix non-MISRA compliant code v2 
This patch is used to fix remaining non compliant code for Intel
SoCFPGA's mailbox and sip driver. These changes include:
- Change non-interface required uint32_t into unsigned int
- Change non-negative variable to unsigned int
- Remove obsolete variable initialization to 0

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5
2020-10-27 11:21:00 +08:00
..
aarch64 intel: Implement platform specific system reset 2 2019-12-30 10:17:04 +08:00
drivers plat: intel: Fix CCU initialization for Agilex 2020-06-08 22:03:48 +00:00
include intel: common: Fix non-MISRA compliant code v2 2020-10-27 11:21:00 +08:00
soc intel: common: Fix non-MISRA compliant code v2 2020-10-27 11:21:00 +08:00
bl2_plat_mem_params_desc.c intel: Platform common code refactor 2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c plat: intel: Additional instruction required to enable global timer 2020-06-08 22:03:54 +00:00
socfpga_image_load.c intel: Implement platform specific system reset 2 2019-12-30 10:17:04 +08:00
socfpga_psci.c intel: Fix argument type for mailbox driver 2020-02-25 16:41:47 +08:00
socfpga_sip_svc.c intel: common: Fix non-MISRA compliant code v2 2020-10-27 11:21:00 +08:00
socfpga_storage.c intel: Refactor common platform code [2/5] 2019-11-28 12:47:58 +08:00
socfpga_topology.c intel: Platform common code refactor 2019-08-01 16:39:27 +08:00