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https://github.com/ARM-software/arm-trusted-firmware.git
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2db1e7663d
This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_PRIVATE_H
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#define SOCFPGA_PRIVATE_H
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#include "socfpga_plat_def.h"
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#define EMMC_DESC_SIZE (1<<20)
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#define EMMC_INIT_PARAMS(base, clk) \
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{ .bus_width = MMC_BUS_WIDTH_4, \
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.clk_rate = (clk), \
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.desc_base = (base), \
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.desc_size = EMMC_DESC_SIZE, \
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.flags = 0, \
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.reg_base = SOCFPGA_MMC_REG_BASE \
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}
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typedef enum {
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BOOT_SOURCE_FPGA = 0,
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BOOT_SOURCE_SDMMC,
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BOOT_SOURCE_NAND,
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BOOT_SOURCE_RSVD,
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BOOT_SOURCE_QSPI
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} boot_source_type;
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/*******************************************************************************
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* Function and variable prototypes
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******************************************************************************/
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void enable_nonsecure_access(void);
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void socfpga_io_setup(int boot_source);
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void socfgpa_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit);
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void socfpga_configure_mmu_el1(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit);
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void socfpga_delay_timer_init(void);
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void socfpga_gic_driver_init(void);
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uint32_t socfpga_get_spsr_for_bl32_entry(void);
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uint32_t socfpga_get_spsr_for_bl33_entry(void);
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unsigned long socfpga_get_ns_image_entrypoint(void);
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void plat_secondary_cpus_bl31_entry(void);
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#endif /* SOCFPGA_PRIVATE_H */
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