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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
136 lines
3.3 KiB
C
136 lines
3.3 KiB
C
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_arch.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "../xlat_tables_private.h"
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#if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
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#error ARMv7 target does not support LPAE MMU descriptors
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#endif
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#define XLAT_TABLE_LEVEL_BASE \
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GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
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#define NUM_BASE_LEVEL_ENTRIES \
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GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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#if ENABLE_ASSERTIONS
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static unsigned long long get_max_supported_pa(void)
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{
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/* Physical address space size for long descriptor format. */
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return (1ULL << 40) - 1ULL;
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}
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#endif /* ENABLE_ASSERTIONS */
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unsigned int xlat_arch_current_el(void)
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{
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/*
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* If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System,
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* SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
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*/
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return 3U;
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}
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uint64_t xlat_arch_get_xn_desc(unsigned int el __unused)
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{
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return UPPER_ATTRS(XN);
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}
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void init_xlat_tables(void)
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{
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unsigned long long max_pa;
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uintptr_t max_va;
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print_mmap();
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init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
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assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
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assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
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}
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void enable_mmu_svc_mon(unsigned int flags)
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{
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unsigned int mair0, ttbcr, sctlr;
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uint64_t ttbr0;
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assert(IS_IN_SECURE());
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assert((read_sctlr() & SCTLR_M_BIT) == 0U);
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/* Set attributes in the right indices of the MAIR */
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mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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ATTR_NON_CACHEABLE_INDEX);
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write_mair0(mair0);
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/* Invalidate TLBs at the current exception level */
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tlbiall();
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/*
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* Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
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*/
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int t0sz = 32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);
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if ((flags & XLAT_TABLE_NC) != 0U) {
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/* Inner & outer non-cacheable non-shareable. */
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
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TTBCR_RGN0_INNER_NC | (uint32_t) t0sz;
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} else {
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/* Inner & outer WBWA & shareable. */
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_RGN0_INNER_WBA | (uint32_t) t0sz;
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}
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ttbcr |= TTBCR_EPD1_BIT;
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write_ttbcr(ttbcr);
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/* Set TTBR0 bits as well */
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ttbr0 = (uintptr_t) base_xlation_table;
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write64_ttbr0(ttbr0);
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write64_ttbr1(0U);
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/*
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* Ensure all translation table writes have drained
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* into memory, the TLB invalidation is complete,
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* and translation register writes are committed
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* before enabling the MMU
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*/
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dsbish();
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isb();
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sctlr = read_sctlr();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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if ((flags & DISABLE_DCACHE) != 0U)
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sctlr &= ~SCTLR_C_BIT;
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else
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sctlr |= SCTLR_C_BIT;
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write_sctlr(sctlr);
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/* Ensure the MMU enable takes effect immediately */
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isb();
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}
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void enable_mmu_direct_svc_mon(unsigned int flags)
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{
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enable_mmu_svc_mon(flags);
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}
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