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Enable the DDR frequency scaling support on i.MX8ULP. Normally, the freq_index define is as below: 0: boot frequency; 1: low frequency(PLL bypassed); 2. high frequency(PLL ON). Currently, DDR DFS only do frequency switching between Low freq and high freq. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428
13 lines
149 B
C
13 lines
149 B
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRAM_H
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#define DRAM_H
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void dram_init(void);
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#endif /* DRAM_H */
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