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https://github.com/ARM-software/arm-trusted-firmware.git
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b4ad365a46
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
76 lines
2 KiB
Makefile
76 lines
2 KiB
Makefile
#
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# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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CSS_USE_SCMI_SDS_DRIVER := 1
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CSS_SGM_BASE := plat/arm/css/sgm
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PLAT_INCLUDES := -I${CSS_SGM_BASE}/include
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PLAT_BL_COMMON_SOURCES := ${CSS_SGM_BASE}/sgm_mmap_config.c \
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${CSS_SGM_BASE}/aarch64/css_sgm_helpers.S
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SECURITY_SOURCES := drivers/arm/tzc/tzc_dmc500.c \
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plat/arm/common/arm_tzc_dmc500.c \
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${CSS_SGM_BASE}/sgm_security.c
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SGM_CPU_SOURCES := lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a75.S
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INTERCONNECT_SOURCES := ${CSS_SGM_BASE}/sgm_interconnect.c
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# GIC-600 configuration
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GICV3_SUPPORT_GIC600 := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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SGM_GIC_SOURCES := ${GICV3_SOURCES} \
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plat/common/plat_gicv3.c \
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plat/arm/common/arm_gicv3.c
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BL1_SOURCES += $(SGM_CPU_SOURCES) \
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${INTERCONNECT_SOURCES} \
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${CSS_SGM_BASE}/sgm_bl1_setup.c \
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${CSS_SGM_BASE}/sgm_plat_config.c \
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drivers/arm/sp805/sp805.c
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BL2_SOURCES += ${SECURITY_SOURCES} \
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${CSS_SGM_BASE}/sgm_plat_config.c
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BL2U_SOURCES += ${SECURITY_SOURCES}
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BL31_SOURCES += $(SGM_CPU_SOURCES) \
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${INTERCONNECT_SOURCES} \
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${SECURITY_SOURCES} \
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${SGM_GIC_SOURCES} \
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${CSS_SGM_BASE}/sgm_topology.c \
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${CSS_SGM_BASE}/sgm_bl31_setup.c \
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${CSS_SGM_BASE}/sgm_plat_config.c
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ifneq (${RESET_TO_BL31},0)
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$(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
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Please set RESET_TO_BL31 to 0.")
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endif
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# sgm uses CCI-500 as Cache Coherent Interconnect
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ARM_CCI_PRODUCT_ID := 500
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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# When building for systems with hardware-assisted coherency, there's no need to
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# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
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USE_COHERENT_MEM := 0
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override ARM_PLAT_MT := 1
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$(eval $(call add_define,SGM_PLAT))
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include plat/arm/common/arm_common.mk
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include plat/arm/board/common/board_common.mk
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include plat/arm/css/common/css_common.mk
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include plat/arm/soc/common/soc_css.mk
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