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https://github.com/ARM-software/arm-trusted-firmware.git
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b4ad365a46
The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
74 lines
2 KiB
Makefile
74 lines
2 KiB
Makefile
#
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# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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N1SDP_BASE := plat/arm/board/n1sdp
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INTERCONNECT_SOURCES := ${N1SDP_BASE}/n1sdp_interconnect.c
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PLAT_INCLUDES := -I${N1SDP_BASE}/include
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N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
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# GIC-600 configuration
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GICV3_SUPPORT_GIC600 := 1
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GICV3_IMPL_GIC600_MULTICHIP := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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N1SDP_GIC_SOURCES := ${GICV3_SOURCES} \
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plat/common/plat_gicv3.c \
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plat/arm/common/arm_gicv3.c \
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PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \
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${N1SDP_BASE}/aarch64/n1sdp_helper.S
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BL1_SOURCES += drivers/arm/sbsa/sbsa.c
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BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
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${INTERCONNECT_SOURCES} \
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${N1SDP_GIC_SOURCES} \
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${N1SDP_BASE}/n1sdp_bl31_setup.c \
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${N1SDP_BASE}/n1sdp_topology.c \
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${N1SDP_BASE}/n1sdp_security.c \
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drivers/arm/css/sds/sds.c
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# TF-A not required to load the SCP Images
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override CSS_LOAD_SCP_IMAGES := 0
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# BL1/BL2 Image not a part of the capsule Image for n1sdp
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override NEED_BL1 := no
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override NEED_BL2 := no
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override NEED_BL2U := no
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#TFA for n1sdp starts from BL31
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override RESET_TO_BL31 := 1
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# 32 bit mode not supported
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override CTX_INCLUDE_AARCH32_REGS := 0
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override ARM_PLAT_MT := 1
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# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
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# SCP during power management operations and for SCP RAM Firmware transfer.
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CSS_USE_SCMI_SDS_DRIVER := 1
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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# When building for systems with hardware-assisted coherency, there's no need to
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# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
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USE_COHERENT_MEM := 0
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# Enable the flag since N1SDP has a system level cache
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NEOVERSE_N1_EXTERNAL_LLC := 1
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include plat/arm/common/arm_common.mk
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include plat/arm/css/common/css_common.mk
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include plat/arm/board/common/board_common.mk
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