nayanpatel-arm b36fe21243 errata: workaround for Cortex-A78 erratum 2132060 ... Cortex-A78 erratum 2132060 is a Cat B erratum that applies to revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open. The workaround is to write the value 2'b11 to the PF_MODE bits in the CPUECTLR_EL1 register which will place the data prefetcher in the most conservative mode instead of disabling it. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401784/latest Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com> Change-Id: If7dec72578633d37d110d103099e406c3a970ff7		2021-10-01 21:21:07 +02:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	errata: workaround for Cortex-A78 erratum 2132060	2021-10-01 21:21:07 +02:00
firmware-design.rst	doc: Correct CPACR.FPEN usage	2020-09-14 02:35:50 +00:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	Mention COT build option in trusted-board-boot-build.rst	2020-03-12 17:11:26 +01:00
trusted-board-boot.rst	Update cryptographic algorithms in TBBR doc	2020-03-12 17:11:25 +01:00