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https://github.com/ARM-software/arm-trusted-firmware.git
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b36e975ea3
This patch adds trbe_disable() which disables Trace buffer access from lower ELs in all security state. This function makes Secure state the owner of Trace buffer and access from EL2/EL1 generate trap exceptions to EL3. Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: If3e3bd621684b3c28f44c3ed2fe3df30b143f8cd
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/trbe.h>
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static void tsb_csync(void)
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{
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/*
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* The assembler does not yet understand the tsb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #18");
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}
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void trbe_enable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSTBE = 0b0
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* Trace Buffer owning Security state is Non-secure state. If FEAT_RME
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* is not implemented, this field is RES0.
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*
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* MDCR_EL3.NSTB = 0b11
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* Allow access of trace buffer control registers from NS-EL1 and
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* NS-EL2, tracing is prohibited in Secure and Realm state (if
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* implemented).
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*/
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mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_disable(cpu_context_t *ctx)
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{
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el3_state_t *state = get_el3state_ctx(ctx);
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u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
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/*
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* MDCR_EL3.NSTBE = 0b0
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* Trace Buffer owning Security state is secure state. If FEAT_RME
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* is not implemented, this field is RES0.
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*
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* MDCR_EL3.NSTB = 0b00
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* Clear these bits to disable access of trace buffer control registers
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* from lower ELs in any security state.
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*/
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mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
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mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
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write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
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}
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void trbe_init_el2_unused(void)
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{
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/*
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* MDCR_EL2.E2TB: Set to zero so that the trace Buffer
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* owning exception level is NS-EL1 and, tracing is
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* prohibited at NS-EL2. These bits are RES0 when
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* FEAT_TRBE is not implemented.
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*/
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write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
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}
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static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
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{
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if (is_feat_trbe_supported()) {
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/*
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* Before switching from normal world to secure world
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* the trace buffers need to be drained out to memory. This is
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* required to avoid an invalid memory access when TTBR is switched
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* for entry to S-EL1.
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*/
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tsb_csync();
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dsbnsh();
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}
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook);
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