arm-trusted-firmware/lib/cpus/aarch64
Soby Mathew b1a9631d81 Optimize barrier usage during Cortex-A57 power down
This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
2014-10-29 17:38:56 +00:00
..
aem_generic.S Add CPU specific crash reporting handlers 2014-08-20 19:14:31 +01:00
cortex_a53.S Add support for level specific cache maintenance operations 2014-10-29 17:38:56 +00:00
cortex_a57.S Optimize barrier usage during Cortex-A57 power down 2014-10-29 17:38:56 +00:00
cpu_helpers.S Apply errata workarounds only when major/minor revisions match. 2014-10-29 17:38:56 +00:00