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Optimize barrier usage during Cortex-A57 power down

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This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
This commit is contained in:
Soby Mathew 2014-09-22 12:15:26 +01:00
parent 7395a725ae
commit b1a9631d81
1 changed files with 1 additions and 1 deletions
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2
lib/cpus/aarch64/cortex_a57.S
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@ -57,7 +57,7 @@ func cortex_a57_disable_l2_prefetch
bic x0, x0, x1
msr CPUECTLR_EL1, x0
isb
dsb sy
dsb ish
ret
/* ---------------------------------------------