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arm-trusted-firmware/plat/intel/soc/agilex/include
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Jit Loon Lim 7931d3322d feat(intel): platform enablement for Agilex5 SoC FPGA 
This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
	1. Added ATF->Zephyr boot option
	2. Added xlat_v2 for MMU
	3. Added ATF->Linux boot option
	4. Added SMP support
	5. Added HPS bridges support
	6. Added EMULATOR support
	7. Added DDR support
	8. Added GICv3 Redistirbution init
	9. Added SDMMC/NAND/Combo Phy support
	10. Updated GIC as secure access
	11. Added CCU driver support
	12. Updated product name -> Agilex5
	13. Updated register address based on y22ww52.2 RTL
	14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
2023-07-05 10:11:22 +08:00
..
agilex_clock_manager.h fix(intel): fix Agilex and N5X clock manager to main PLL C0 2023-04-14 09:19:31 +08:00
agilex_memory_controller.h feat(intel): restructure sys mgr for Agilex 2023-05-23 21:13:05 +08:00
agilex_mmc.h plat: intel: set DRVSEL and SMPLSEL for DWMMC 2020-06-08 22:03:34 +00:00
agilex_pinmux.h feat(intel): setup FPGA interface for Agilex 2022-11-22 23:35:36 +08:00
agilex_system_manager.h feat(intel): restructure sys mgr for Agilex 2023-05-23 21:13:05 +08:00
socfpga_plat_def.h feat(intel): platform enablement for Agilex5 SoC FPGA 2023-07-05 10:11:22 +08:00