Jit Loon Lim 7931d3322d feat(intel): platform enablement for Agilex5 SoC FPGA ... This patch is used to enable platform enablement for Agilex5 SoC FPGA. New feature: 1. Added ATF->Zephyr boot option 2. Added xlat_v2 for MMU 3. Added ATF->Linux boot option 4. Added SMP support 5. Added HPS bridges support 6. Added EMULATOR support 7. Added DDR support 8. Added GICv3 Redistirbution init 9. Added SDMMC/NAND/Combo Phy support 10. Updated GIC as secure access 11. Added CCU driver support 12. Updated product name -> Agilex5 13. Updated register address based on y22ww52.2 RTL 14. Updated system counter freq to 400MHz Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009		2023-07-05 10:11:22 +08:00
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include	feat(intel): platform enablement for Agilex5 SoC FPGA	2023-07-05 10:11:22 +08:00
soc	feat(intel): restructure sys mgr for Agilex	2023-05-23 21:13:05 +08:00
bl2_plat_setup.c	feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands	2022-05-11 17:43:16 +08:00
bl31_plat_setup.c	fix(tree): correct some typos	2023-05-09 15:57:12 +01:00
platform.mk	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00