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5541bb3f61
This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
69 lines
3 KiB
Markdown
69 lines
3 KiB
Markdown
ARM CPU Specific Build Macros
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=============================
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Contents
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--------
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1. Introduction
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2. CPU Errata Workarounds
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3. CPU Specific optimizations
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1. Introduction
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----------------
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This document describes the various build options present in the CPU specific
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operations framework to enable errata workarounds and to enable optimizations
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for a specific CPU on a platform.
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2. CPU Errata Workarounds
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--------------------------
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ARM Trusted Firmware exports a series of build flags which control the
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errata workarounds that are applied to each CPU by the reset handler. The
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errata details can be found in the CPU specifc errata documents published
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by ARM. The errata workarounds are implemented for a particular revision
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or a set of processor revisions. This is checked by reset handler at runtime.
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Each errata workaround is identified by its `ID` as specified in the processor's
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errata notice document. The format of the define used to enable/disable the
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errata is `ERRATA_<Processor name>_<ID>` where the `Processor name`
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is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU.
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All workarounds are disabled by default. The platform is reponsible for
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enabling these workarounds according to its requirement by defining the
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errata workaround build flags in the platform specific makefile. In case
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these workarounds are enabled for the wrong CPU revision then the errata
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workaround is not applied. In the DEBUG build, this is indicated by
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printing a warning to the crash console.
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In the current implementation, a platform which has more than 1 variant
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with different revisions of a processor has no runtime mechanism available
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for it to specify which errata workarounds should be enabled or not.
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The value of the build flags are 0 by default, that is, disabled. Any other
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value will enable it.
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For Cortex-A57, following errata build flags are defined :
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* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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3. CPU Specific optimizations
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------------------------------
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This section describes some of the optimizations allowed by the CPU micro
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architecture that can be enabled by the platform as desired.
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* `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the
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Cortex-A57 cluster power down sequence by not flushing the Level 1 data
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cache. The L1 data cache and the L2 unified cache are inclusive. A flush
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of the L2 by set/way flushes any dirty lines from the L1 as well. This
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is a known safe deviation from the Cortex-A57 TRM defined power down
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sequence. Each Cortex-A57 based platform must make its own decision on
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whether to use the optimization.
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._
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