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https://github.com/ARM-software/arm-trusted-firmware.git
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af6491f85c
The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been fixed. The types tzc_region_attributes_t and tzc_action_t have been removed and replaced by unsigned int because it is not allowed to do logical operations on enums. Also, fix some address definitions in arm_def.h. Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
218 lines
6.7 KiB
C
218 lines
6.7 KiB
C
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC_COMMON_PRIVATE_H
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#define TZC_COMMON_PRIVATE_H
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#include <arch.h>
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#include <arch_helpers.h>
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#include <mmio.h>
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#include <tzc_common.h>
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#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_action( \
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uintptr_t base, \
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unsigned int action) \
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{ \
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mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \
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action); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_base( \
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uintptr_t base, \
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unsigned int region_no, \
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unsigned long long region_base) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
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(uint32_t)region_base); \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \
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(uint32_t)(region_base >> 32)); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_top( \
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uintptr_t base, \
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unsigned int region_no, \
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unsigned long long region_top) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET \
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(TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
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(uint32_t)region_top); \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
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(uint32_t)(region_top >> 32)); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_attributes( \
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uintptr_t base, \
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unsigned int region_no, \
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unsigned int attr) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_ATTR_0_OFFSET, \
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attr); \
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}
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#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \
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static inline void _tzc##fn_name##_write_region_id_access( \
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uintptr_t base, \
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unsigned int region_no, \
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unsigned int val) \
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{ \
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mmio_write_32(base + \
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TZC_REGION_OFFSET( \
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TZC_##macro_name##_REGION_SIZE, \
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region_no) + \
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TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \
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val); \
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}
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/*
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* It is used to program region 0 ATTRIBUTES and ACCESS register.
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*/
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#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \
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static void _tzc##fn_name##_configure_region0(uintptr_t base, \
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unsigned int sec_attr, \
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unsigned int ns_device_access) \
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{ \
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assert(base != 0U); \
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VERBOSE("TrustZone : Configuring region 0 " \
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"(TZC Interface Base=0x%lx sec_attr=0x%x," \
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" ns_devs=0x%x)\n", base, \
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sec_attr, ns_device_access); \
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\
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/* Set secure attributes on region 0 */ \
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_tzc##fn_name##_write_region_attributes(base, 0, \
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sec_attr << TZC_REGION_ATTR_SEC_SHIFT); \
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\
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/***************************************************/ \
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/* Specify which non-secure devices have permission*/ \
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/* to access region 0. */ \
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/***************************************************/ \
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_tzc##fn_name##_write_region_id_access(base, \
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0, \
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ns_device_access); \
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}
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/*
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* It is used to program a region from 1 to 8 in the TrustZone controller.
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* NOTE:
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* Region 0 is special; it is preferable to use
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* ##fn_name##_configure_region0 for this region (see comment for
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* that function).
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*/
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#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \
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static void _tzc##fn_name##_configure_region(uintptr_t base, \
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unsigned int filters, \
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unsigned int region_no, \
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unsigned long long region_base, \
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unsigned long long region_top, \
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unsigned int sec_attr, \
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unsigned int nsaid_permissions) \
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{ \
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assert(base != 0U); \
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VERBOSE("TrustZone : Configuring region " \
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"(TZC Interface Base: 0x%lx, region_no = %u)" \
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"...\n", base, region_no); \
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VERBOSE("TrustZone : ... base = %llx, top = %llx," \
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"\n", region_base, region_top); \
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VERBOSE("TrustZone : ... sec_attr = 0x%x," \
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" ns_devs = 0x%x)\n", \
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sec_attr, nsaid_permissions); \
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\
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/***************************************************/ \
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/* Inputs look ok, start programming registers. */ \
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/* All the address registers are 32 bits wide and */ \
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/* have a LOW and HIGH */ \
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/* component used to construct an address up to a */ \
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/* 64bit. */ \
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/***************************************************/ \
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_tzc##fn_name##_write_region_base(base, \
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region_no, region_base); \
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_tzc##fn_name##_write_region_top(base, \
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region_no, region_top); \
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\
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/* Enable filter to the region and set secure attributes */\
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_tzc##fn_name##_write_region_attributes(base, \
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region_no, \
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(sec_attr << TZC_REGION_ATTR_SEC_SHIFT) |\
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(filters << TZC_REGION_ATTR_F_EN_SHIFT));\
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\
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/***************************************************/ \
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/* Specify which non-secure devices have permission*/ \
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/* to access this region. */ \
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/***************************************************/ \
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_tzc##fn_name##_write_region_id_access(base, \
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region_no, \
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nsaid_permissions); \
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}
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static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
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{
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unsigned int id;
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id = mmio_read_32(base + PID0_OFF);
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/* Masks DESC part in PID1 */
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id |= ((mmio_read_32(base + PID1_OFF) & 0xFU) << 8U);
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return id;
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}
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#if ENABLE_ASSERTIONS
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#ifdef AARCH32
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static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width)
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{
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/*
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* Assume at least 32 bit wide address and initialize the max.
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* This function doesn't use 64-bit integer arithmetic to avoid
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* having to implement additional compiler library functions.
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*/
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unsigned long long addr_mask = 0xFFFFFFFFU;
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uint32_t *addr_ptr = (uint32_t *)&addr_mask;
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assert(addr_width >= 32U);
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/* This logic works only on little - endian platforms */
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assert((read_sctlr() & SCTLR_EE_BIT) == 0U);
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/*
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* If required address width is greater than 32, populate the higher
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* 32 bits of the 64 bit field with the max address.
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*/
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if (addr_width > 32U)
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*(addr_ptr + 1U) = ((1U << (addr_width - 32U)) - 1U);
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return addr_mask;
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}
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#else
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static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width)
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{
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return UINT64_MAX >> (64U - addr_width);
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}
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#endif /* AARCH32 */
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#endif /* ENABLE_ASSERTIONS */
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#endif /* TZC_COMMON_PRIVATE_H */
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