Varun Wadekar cd0ea1842f cpus: higher performance non-cacheable load forwarding ... The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-02-20 09:25:45 -08:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	doc: Convert internal links to RST format	2019-10-08 15:58:03 +00:00
cpu-specific-build-macros.rst	cpus: higher performance non-cacheable load forwarding	2020-02-20 09:25:45 -08:00
firmware-design.rst	Update docs with PMU security information	2020-02-12 13:08:20 +00:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	doc: Convert internal links to RST format	2019-10-08 15:58:03 +00:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	Adds option to read ROTPK from registers for FVP	2020-02-06 16:58:53 +00:00
trusted-board-boot.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00