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Update docs with PMU security information
This patch adds information on the PMU configuration registers and security considerations related to the PMU. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I36b15060b9830a77d3f47f293c0a6dafa3c581fb
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Petre-Ionut Tudor
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4 changed files with 261 additions and 3 deletions
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@ -2696,13 +2696,13 @@ kernel at boot time. These can be found in the ``fdts`` directory.
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--------------
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*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
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*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
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.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
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.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
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.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html
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.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
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.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
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.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
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@ -8,7 +8,8 @@ Performance & Testing
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psci-performance-juno
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tsp
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performance-monitoring-unit
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--------------
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*Copyright (c) 2019, Arm Limited. All rights reserved.*
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*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
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158
docs/perf/performance-monitoring-unit.rst
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158
docs/perf/performance-monitoring-unit.rst
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@ -0,0 +1,158 @@
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Performance Monitoring Unit
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===========================
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The Performance Monitoring Unit (PMU) allows recording of architectural and
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microarchitectural events for profiling purposes.
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This document gives an overview of the PMU counter configuration to assist with
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implementation and to complement the PMU security guidelines given in the
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:ref:`Secure Development Guidelines` document.
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.. note::
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This section applies to Armv8-A implementations which have version 3
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of the Performance Monitors Extension (PMUv3).
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PMU Counters
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------------
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The PMU makes 32 counters available at all privilege levels:
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- 31 programmable event counters: ``PMEVCNTR<n>``, where ``n`` is ``0`` to
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``30``.
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- A dedicated cycle counter: ``PMCCNTR``.
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Architectural mappings
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~~~~~~~~~~~~~~~~~~~~~~
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+--------------+---------+----------------------------+
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| Counters | State | System Register Name |
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+==============+=========+============================+
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| | AArch64 | ``PMEVCNTR<n>_EL0[63*:0]`` |
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| Programmable +---------+----------------------------+
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| | AArch32 | ``PMEVCNTR<n>[31:0]`` |
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+--------------+---------+----------------------------+
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| | AArch64 | ``PMCCNTR_EL0[63:0]`` |
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| Cycle +---------+----------------------------+
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| | AArch32 | ``PMCCNTR[63:0]`` |
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+--------------+---------+----------------------------+
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.. note::
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Bits [63:32] are only available if ARMv8.5-PMU is implemented. Refer to the
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`Arm ARM`_ for a detailed description of ARMv8.5-PMU features.
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Configuring the PMU for counting events
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---------------------------------------
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Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
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configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
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an identical function and bit field layout as ``PMEVTYPER<n>``. In addition,
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the counters are enabled (permitted to increment) via the ``PMCNTENSET`` and
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``PMCR`` registers. These can be accessed at all privilege levels.
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Architectural mappings
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~~~~~~~~~~~~~~~~~~~~~~
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+-----------------------------+------------------------+
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| AArch64 | AArch32 |
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+=============================+========================+
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| ``PMEVTYPER<n>_EL0[63*:0]`` | ``PMEVTYPER<n>[31:0]`` |
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+-----------------------------+------------------------+
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| ``PMCCFILTR_EL0[63*:0]`` | ``PMCCFILTR[31:0]`` |
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+-----------------------------+------------------------+
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| ``PMCNTENSET_EL0[63*:0]`` | ``PMCNTENSET[31:0]`` |
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+-----------------------------+------------------------+
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| ``PMCR_EL0[63*:0]`` | ``PMCR[31:0]`` |
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+-----------------------------+------------------------+
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.. note::
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Bits [63:32] are reserved.
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Relevant register fields
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~~~~~~~~~~~~~~~~~~~~~~~~
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For ``PMEVTYPER<n>_EL0``/``PMEVTYPER<n>`` and ``PMCCFILTR_EL0/PMCCFILTR``, the
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most important fields are:
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- ``P``:
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- Bit 31.
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- If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
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- ``NSK``:
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- Bit 29.
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- If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
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Non-secure EL1.
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- Reserved if EL3 not implemented.
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- ``NSH``:
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- Bit 27.
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- If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
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- Reserved if EL2 not implemented.
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- ``SH``:
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- Bit 24.
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- If different to the ``NSH`` bit it enables the associated ``PMEVCNTR<n>``
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at Secure EL2.
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- Reserved if Secure EL2 not implemented.
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- ``M``:
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- Bit 26.
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- If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
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EL3.
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- ``evtCount[15:10]``:
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- Extension to ``evtCount[9:0]``. Reserved unless ARMv8.1-PMU implemented.
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- ``evtCount[9:0]``:
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- The event number that the associated ``PMEVCNTR<n>`` will count.
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For ``PMCNTENSET_EL0``/``PMCNTENSET``, the most important fields are:
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- ``P[30:0]``:
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- Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
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- The effects of ``PMEVTYPER<n>`` are applied on top of this.
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In other words, the counter will not increment at any privilege level or
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security state unless it is enabled here.
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- ``C``:
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- Bit 31.
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- If set to ``1`` enables the cycle counter ``PMCCNTR``.
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For ``PMCR``/``PMCR_EL0``, the most important fields are:
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- ``DP``:
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- Bit 5.
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- If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
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counting (by ``PMEVCNTR<n>``) is prohibited (e.g. EL2 and the Secure
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world).
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- If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
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therefore will be able to count where the programmable counters are
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prohibited.
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- ``E``:
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- Bit 0.
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- Enables/disables counting altogether.
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- The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
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In other words, if this bit is ``0`` then no counters will increment
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regardless of how the other PMU system registers or bit fields are
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configured.
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.. rubric:: References
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- `Arm ARM`_
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--------------
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*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
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.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
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@ -25,6 +25,99 @@ The secure world **should never** crash or become unusable due to receiving too
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many normal world requests (a *Denial of Service* or *DoS* attack). It should
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have a mechanism for throttling or ignoring normal world requests.
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Preventing Secure-world timing information leakage via PMU counters
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The Secure world needs to implement some defenses to prevent the Non-secure
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world from making it leak timing information. In general, higher privilege
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levels must defend from those below when the PMU is treated as an attack
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vector.
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Refer to the :ref:`Performance Monitoring Unit` guide for detailed information
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on the PMU registers.
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Timing leakage attacks from the Non-secure world
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Since the Non-secure world has access to the ``PMCR`` register, it can
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configure the PMU to increment counters at any exception level and in both
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Secure and Non-secure state. Thus, it attempts to leak timing information from
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the Secure world.
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Shown below is an example of such a configuration:
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- ``PMEVTYPER0_EL0`` and ``PMCCFILTR_EL0``:
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- Set ``P`` to ``0``.
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- Set ``NSK`` to ``1``.
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- Set ``M`` to ``0``.
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- Set ``NSH`` to ``0``.
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- Set ``SH`` to ``1``.
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- ``PMCNTENSET_EL0``:
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- Set ``P[0]`` to ``1``.
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- Set ``C`` to ``1``.
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- ``PMCR_EL0``:
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- Set ``DP`` to ``0``.
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- Set ``E`` to ``1``.
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This configuration instructs ``PMEVCNTR0_EL0`` and ``PMCCNTR_EL0`` to increment
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at Secure EL1, Secure EL2 (if implemented) and EL3.
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Since the Non-secure world has fine-grained control over where (at which
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exception levels) it instructs counters to increment, obtaining event counts
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would allow it to carry out side-channel timing attacks against the Secure
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world. Examples include Spectre, Meltdown, as well as extracting secrets from
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cryptographic algorithms with data-dependent variations in their execution
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time.
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Secure world mitigation strategies
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The ``MDCR_EL3`` register allows EL3 to configure the PMU (among other things).
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The `Arm ARM`_ details all of the bit fields in this register, but for the PMU
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there are two bits which determine the permissions of the counters:
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- ``SPME`` for the programmable counters.
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- ``SCCD`` for the cycle counter.
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Depending on the implemented features, the Secure world can prohibit counting
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in AArch64 state via the following:
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- ARMv8.2-Debug not implemented:
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- Prohibit general event counters and the cycle counter:
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``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1 && !ExternalSecureNoninvasiveDebugEnabled()``.
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- ``MDCR_EL3.SPME`` resets to ``0``, so by default general events should
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not be counted in the Secure world.
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- The ``PMCR_EL0.DP`` bit therefore needs to be set to ``1`` when EL3 is
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entered and ``PMCR_EL0`` needs to be saved and restored in EL3.
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- ``ExternalSecureNoninvasiveDebugEnabled()`` is an authentication
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interface which is implementation-defined unless ARMv8.4-Debug is
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implemented. The `Arm ARM`_ has detailed information on this topic.
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- The only other way is to disable the ``PMCR_EL0.E`` bit upon entering
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EL3, which disables counting altogether.
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- ARMv8.2-Debug implemented:
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- Prohibit general event counters: ``MDCR_EL3.SPME == 0``.
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- Prohibit cycle counter: ``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1``.
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``PMCR_EL0`` therefore needs to be saved and restored in EL3.
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- ARMv8.5-PMU implemented:
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- Prohibit general event counters: as in ARMv8.2-Debug.
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- Prohibit cycle counter: ``MDCR_EL3.SCCD == 1``
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In Aarch32 execution state the ``MDCR_EL3`` alias is the ``SDCR`` register,
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which has some of the bit fields of ``MDCR_EL3``, most importantly the ``SPME``
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and ``SCCD`` bits.
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Build options
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-------------
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@ -71,6 +164,12 @@ Several build options can be used to check for security issues. Refer to the
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NB: The ``Werror`` flag is enabled by default in TF-A and can be disabled by
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setting the ``E`` build flag to 0.
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.. rubric:: References
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- `Arm ARM`_
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--------------
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*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
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.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
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