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https://github.com/ARM-software/arm-trusted-firmware.git
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ade92a64e4
On receiving CPU power down callback, TF-A raises SGI interrupt to all active cores to power down each active cores. Add handler for this SGI IRQ. By default TF-A uses SGI 6 for CPU power down request. This can be configurable through CPU_PWRDWN_SGI build flag. e.g., If user wants to use SGI 7 instead of SGI 6 then provide build flag CPU_PWRDWN_SGI=7 Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd
129 lines
3.9 KiB
Makefile
129 lines
3.9 KiB
Makefile
# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
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# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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PLAT_PATH := plat/xilinx/versal_net
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# A78 Erratum for SoC
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ERRATA_A78_AE_1941500 := 1
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ERRATA_A78_AE_1951502 := 1
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ERRATA_A78_AE_2376748 := 1
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ERRATA_A78_AE_2395408 := 1
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override PROGRAMMABLE_RESET_ADDRESS := 1
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PSCI_EXTENDED_STATE_ID := 1
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SEPARATE_CODE_AND_RODATA := 1
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override RESET_TO_BL31 := 1
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PL011_GENERIC_UART := 1
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IPI_CRC_CHECK := 0
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GIC_ENABLE_V4_EXTN := 0
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GICV3_SUPPORT_GIC600 := 1
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TFA_NO_PM := 0
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CPU_PWRDWN_SGI ?= 6
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$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI}))
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override CTX_INCLUDE_AARCH32_REGS := 0
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ifdef TFA_NO_PM
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$(eval $(call add_define,TFA_NO_PM))
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endif
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ifdef VERSAL_NET_ATF_MEM_BASE
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$(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
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ifndef VERSAL_NET_ATF_MEM_SIZE
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$(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
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endif
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$(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
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ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE
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$(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE))
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endif
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endif
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ifdef VERSAL_NET_BL32_MEM_BASE
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$(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
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ifndef VERSAL_NET_BL32_MEM_SIZE
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$(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
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endif
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$(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
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endif
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ifdef IPI_CRC_CHECK
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$(eval $(call add_define,IPI_CRC_CHECK))
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endif
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USE_COHERENT_MEM := 0
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HW_ASSISTED_COHERENCY := 1
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VERSAL_NET_CONSOLE ?= pl011
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ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
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else
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$(error Please define VERSAL_NET_CONSOLE)
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endif
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$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE}))
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ifdef XILINX_OF_BOARD_DTB_ADDR
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$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
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endif
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# enable assert() for release/debug builds
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ENABLE_ASSERTIONS := 1
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iplat/xilinx/common/include/ \
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-Iplat/xilinx/common/ipi_mailbox_service/ \
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-I${PLAT_PATH}/include/ \
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-Iplat/xilinx/versal/pm_service/
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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include lib/libfdt/libfdt.mk
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PLAT_BL_COMMON_SOURCES := \
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drivers/arm/dcc/dcc_console.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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${GICV3_SOURCES} \
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drivers/arm/pl011/aarch64/pl011_console.S \
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plat/common/aarch64/crash_console_helpers.S \
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plat/arm/common/arm_common.c \
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plat/common/plat_gicv3.c \
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${PLAT_PATH}/aarch64/versal_net_helpers.S \
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${PLAT_PATH}/aarch64/versal_net_common.c \
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${PLAT_PATH}/plat_topology.c \
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${XLAT_TABLES_LIB_SRCS}
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BL31_SOURCES += drivers/arm/cci/cci.c \
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_a78.S \
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plat/common/plat_psci_common.c
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ifeq ($(TFA_NO_PM), 0)
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BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \
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plat/xilinx/common/pm_service/pm_ipi.c \
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${PLAT_PATH}/plat_psci_pm.c \
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plat/xilinx/common/pm_service/pm_svc_main.c \
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${PLAT_PATH}/pm_service/pm_client.c \
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${PLAT_PATH}/versal_net_ipi.c
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else
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BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
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endif
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BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
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plat/xilinx/common/plat_startup.c \
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plat/xilinx/common/plat_console.c \
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plat/xilinx/common/plat_clkfunc.c \
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plat/xilinx/common/ipi.c \
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plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
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plat/xilinx/common/versal.c \
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${PLAT_PATH}/bl31_versal_net_setup.c \
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common/fdt_fixup.c \
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common/fdt_wrappers.c \
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plat/arm/common/arm_gicv3.c \
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${LIBFDT_SRCS} \
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${PLAT_PATH}/sip_svc_setup.c \
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${XLAT_TABLES_LIB_SRCS}
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