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https://github.com/ARM-software/arm-trusted-firmware.git
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ade92a64e4
On receiving CPU power down callback, TF-A raises SGI interrupt to all active cores to power down each active cores. Add handler for this SGI IRQ. By default TF-A uses SGI 6 for CPU power down request. This can be configurable through CPU_PWRDWN_SGI build flag. e.g., If user wants to use SGI 7 instead of SGI 6 then provide build flag CPU_PWRDWN_SGI=7 Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd
134 lines
4.4 KiB
C
134 lines
4.4 KiB
C
/*
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* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat_common.h>
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#include "versal_net_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE U(0x440)
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#define PLATFORM_CLUSTER_COUNT U(4)
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#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#ifndef VERSAL_NET_ATF_MEM_BASE
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# define BL31_BASE U(0xBBF00000)
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# define BL31_LIMIT U(0xBC000000)
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#else
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# define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE)
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# define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE)
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# ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE
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# define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \
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VERSAL_NET_ATF_MEM_PROGBITS_SIZE)
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# endif
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#endif
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#ifndef VERSAL_NET_BL32_MEM_BASE
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# define BL32_BASE U(0x60000000)
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# define BL32_LIMIT U(0x80000000)
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#else
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# define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE)
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# define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE)
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#endif
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/*******************************************************************************
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* BL33 specific defines.
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******************************************************************************/
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#ifndef PRELOADED_BL33_BASE
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# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
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#else
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# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
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#endif
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/*******************************************************************************
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* TSP specific defines.
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******************************************************************************/
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE)
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/* ID of the secure physical generic timer interrupt used by the TSP */
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#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U)
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#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
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#define PLAT_OCM_BASE U(0xBBF00000)
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#define PLAT_OCM_LIMIT U(0xBC000000)
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#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
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#ifndef MAX_MMAP_REGIONS
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#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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#define MAX_MMAP_REGIONS 9
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#else
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#define MAX_MMAP_REGIONS 8
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#endif
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#endif
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#ifndef MAX_XLAT_TABLES
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#define MAX_XLAT_TABLES U(9)
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#endif
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_ARM_GICD_BASE U(0xE2000000)
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#define PLAT_ARM_GICR_BASE U(0xE2060000)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_VERSAL_NET_IPI_IRQ 89
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#define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define IRQ_MAX 200U
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#endif /* PLATFORM_DEF_H */
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