Jay Buddhabhatti ade92a64e4 feat(xilinx): add handler for power down req sgi irq ... On receiving CPU power down callback, TF-A raises SGI interrupt to all active cores to power down each active cores. Add handler for this SGI IRQ. By default TF-A uses SGI 6 for CPU power down request. This can be configurable through CPU_PWRDWN_SGI build flag. e.g., If user wants to use SGI 7 instead of SGI 6 then provide build flag CPU_PWRDWN_SGI=7 Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd		2024-01-09 04:15:27 -08:00
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aarch64	refactor(xilinx): move plat_get_syscnt_freq2 to common file	2024-01-04 15:29:49 +01:00
include	feat(xilinx): add handler for power down req sgi irq	2024-01-09 04:15:27 -08:00
pm_service	chore(xilinx): reorder include files as per TF-A guidelines	2023-06-27 10:14:09 +05:30
tsp	feat(versal): add tsp support	2023-11-02 06:04:56 +01:00
bl31_versal_setup.c	fix(versal): initialize cntfrq_el0 register	2024-01-04 15:29:18 +01:00
plat_psci.c	chore(xilinx): reorder include files as per TF-A guidelines	2023-06-27 10:14:09 +05:30
plat_topology.c	style(xilinx): replace ARM by Arm in copyrights	2023-04-14 08:54:37 +02:00
plat_versal.c	chore(xilinx): reorder include files as per TF-A guidelines	2023-06-27 10:14:09 +05:30
platform.mk	feat(xilinx): add handler for power down req sgi irq	2024-01-09 04:15:27 -08:00
sip_svc_setup.c	chore(xilinx): follow kernel doc format for functional documentation	2023-06-23 08:07:13 +01:00
versal_gicv3.c	fix(xilinx): rename macros to align with ARM	2024-01-09 00:38:21 -08:00
versal_ipi.c	fix(versal): make pmc ipi channel as secure	2023-08-08 12:52:16 +02:00