Soby Mathew add403514d Add CPU specific power management operations ... This patch adds CPU core and cluster power down sequences to the CPU specific operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and generic AEM sequences have been added. The latter is suitable for the Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is saved in the per-cpu data so that it can be easily accessed during power down seqeunces. An optional platform API has been introduced to allow a platform to disable the Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak definition of this function (plat_disable_acp()) does not take any action. It should be overriden with a strong definition if the ACP is present on a platform. Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d		2014-08-20 19:14:31 +01:00
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bl31_arch_setup.c	Unmask SError interrupt and clear SCR_EL3.EA bit	2014-08-15 10:21:50 +01:00
bl31_entrypoint.S	Add CPU specific power management operations	2014-08-20 19:14:31 +01:00
context.S	Optimize EL3 register state stored in cpu_context structure	2014-07-31 10:09:58 +01:00
cpu_data.S	Per-cpu data cache restructuring	2014-06-16 21:30:32 +01:00
crash_reporting.S	Add CPUECTLR_EL1 and Snoop Control register to crash reporting	2014-07-28 11:03:20 +01:00
runtime_exceptions.S	Unmask SError interrupt and clear SCR_EL3.EA bit	2014-08-15 10:21:50 +01:00